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[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier
See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591 Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35424 llvm-svn: 308740
This commit is contained in:
Dmitry Preobrazhensky
parent
030b7675c5
commit
a902d05ab9
@ -174,6 +174,14 @@ private:
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bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp) const;
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bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3OpSel0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp) const;
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bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp) const;
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void SelectADD_SUB_I64(SDNode *N);
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void SelectUADDO_USUBO(SDNode *N);
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void SelectDIV_SCALE(SDNode *N);
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@ -1864,6 +1872,42 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PMods0(SDValue In, SDValue &Src,
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return SelectVOP3PMods(In, Src, SrcMods);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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Src = In;
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// FIXME: Handle op_sel
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SrcMods = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3OpSel0(SDValue In, SDValue &Src,
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SDValue &SrcMods,
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SDValue &Clamp) const {
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SDLoc SL(In);
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// FIXME: Handle clamp
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Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
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return SelectVOP3OpSel(In, Src, SrcMods);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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// FIXME: Handle op_sel
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return SelectVOP3Mods(In, Src, SrcMods);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods0(SDValue In, SDValue &Src,
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SDValue &SrcMods,
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SDValue &Clamp) const {
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SDLoc SL(In);
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// FIXME: Handle clamp
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Clamp = CurDAG->getTargetConstant(0, SL, MVT::i32);
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return SelectVOP3OpSelMods(In, Src, SrcMods);
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}
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void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
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const AMDGPUTargetLowering& Lowering =
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*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
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@ -1060,6 +1060,7 @@ public:
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
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OptionalImmIndexMap &OptionalIdx);
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void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
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@ -2688,7 +2689,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseOperandArrayWithPrefix(
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// FIXME: How to verify the number of elements matches the number of src
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// operands?
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for (int I = 0; I < 3; ++I) {
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for (int I = 0; I < 4; ++I) {
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if (I != 0) {
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if (getLexer().is(AsmToken::RBrac))
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break;
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@ -4088,6 +4089,30 @@ OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands)
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return MatchOperand_NoMatch;
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}
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void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands) {
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cvtVOP3P(Inst, Operands);
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int Opc = Inst.getOpcode();
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int SrcNum;
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const int Ops[] = { AMDGPU::OpName::src0,
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AMDGPU::OpName::src1,
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AMDGPU::OpName::src2 };
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for (SrcNum = 0;
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SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1;
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++SrcNum);
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assert(SrcNum > 0);
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int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
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unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
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if ((OpSel & (1 << SrcNum)) != 0) {
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int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
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uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
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Inst.getOperand(ModIdx).setImm(ModVal | SISrcMods::DST_OP_SEL);
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}
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}
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static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
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// 1. This operand is input modifiers
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return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
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@ -4172,7 +4197,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
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int Opc = Inst.getOpcode();
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addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
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addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1);
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int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
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if (OpSelHiIdx != -1) {
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addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1);
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}
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int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);
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if (NegLoIdx != -1) {
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@ -4188,13 +4217,16 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
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AMDGPU::OpName::src2_modifiers };
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int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
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int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
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unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
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unsigned OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();
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unsigned OpSelHi = 0;
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unsigned NegLo = 0;
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unsigned NegHi = 0;
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if (OpSelHiIdx != -1) {
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OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();
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}
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if (NegLoIdx != -1) {
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int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);
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NegLo = Inst.getOperand(NegLoIdx).getImm();
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@ -803,7 +803,8 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
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}
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}
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static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod) {
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static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
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bool HasDstSel) {
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int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
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for (int I = 0; I < NumOps; ++I) {
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@ -811,11 +812,16 @@ static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod) {
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return false;
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}
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if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
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return false;
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return true;
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}
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static void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
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raw_ostream &O) {
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void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
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StringRef Name,
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unsigned Mod,
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raw_ostream &O) {
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unsigned Opc = MI->getOpcode();
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int NumOps = 0;
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int Ops[3];
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@ -830,7 +836,12 @@ static void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
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Ops[NumOps++] = MI->getOperand(Idx).getImm();
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}
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if (allOpsDefaultValue(Ops, NumOps, Mod))
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const bool HasDstSel =
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NumOps > 0 &&
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Mod == SISrcMods::OP_SEL_0 &&
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MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
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if (allOpsDefaultValue(Ops, NumOps, Mod, HasDstSel))
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return;
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O << Name;
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@ -841,6 +852,10 @@ static void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
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O << !!(Ops[I] & Mod);
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}
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if (HasDstSel) {
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O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
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}
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O << ']';
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}
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@ -127,6 +127,8 @@ private:
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printSDWADstUnused(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printPackedModifier(const MCInst *MI, StringRef Name, unsigned Mod,
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raw_ostream &O);
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void printOpSel(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printOpSelHi(const MCInst *MI, unsigned OpNo,
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@ -67,7 +67,8 @@ enum : uint64_t {
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SCALAR_STORE = UINT64_C(1) << 39,
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FIXED_SIZE = UINT64_C(1) << 40,
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VOPAsmPrefer32Bit = UINT64_C(1) << 41,
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HasFPClamp = UINT64_C(1) << 42
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HasFPClamp = UINT64_C(1) << 42,
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VOP3_OPSEL = UINT64_C(1) << 43
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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@ -137,7 +138,8 @@ namespace SISrcMods {
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SEXT = 1 << 0, // Integer sign-extend modifier
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NEG_HI = ABS, // Floating-point negate high packed component modifier.
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OP_SEL_0 = 1 << 2,
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OP_SEL_1 = 1 << 3
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OP_SEL_1 = 1 << 3,
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DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
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};
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}
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@ -83,6 +83,10 @@ class InstSI <dag outs, dag ins, string asm = "",
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// the clamp modifier has floating point semantics.
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field bit FPClamp = 0;
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// This bit indicates that this is a VOP3 opcode which supports op_sel
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// modifier (gfx9 only).
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field bit VOP3_OPSEL = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = SALU;
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let TSFlags{1} = VALU;
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@ -127,6 +131,7 @@ class InstSI <dag outs, dag ins, string asm = "",
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let TSFlags{40} = FixedSize;
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let TSFlags{41} = VOPAsmPrefer32Bit;
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let TSFlags{42} = FPClamp;
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let TSFlags{43} = VOP3_OPSEL;
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let SchedRW = [Write32Bit];
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@ -659,6 +659,15 @@ class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass>
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def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
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def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
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class OpSelModsMatchClass : AsmOperandClass {
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let Name = "OpSelMods";
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let ParserMethod = "parseRegOrImm";
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let PredicateMethod = "isRegOrImm";
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}
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def IntOpSelModsMatchClass : OpSelModsMatchClass;
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def IntOpSelMods : InputMods<IntOpSelModsMatchClass>;
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def FPRegSDWAInputModsMatchClass : AsmOperandClass {
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let Name = "SDWARegWithFPInputMods";
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let ParserMethod = "parseRegWithFPInputMods";
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@ -750,6 +759,11 @@ def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
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def VOP3PMods : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
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def VOP3PMods0 : ComplexPattern<untyped, 3, "SelectVOP3PMods0">;
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def VOP3OpSel : ComplexPattern<untyped, 2, "SelectVOP3OpSel">;
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def VOP3OpSel0 : ComplexPattern<untyped, 3, "SelectVOP3OpSel0">;
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def VOP3OpSelMods : ComplexPattern<untyped, 2, "SelectVOP3OpSelMods">;
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def VOP3OpSelMods0 : ComplexPattern<untyped, 3, "SelectVOP3OpSelMods0">;
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//===----------------------------------------------------------------------===//
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// SI assembler operands
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@ -771,6 +785,7 @@ def SRCMODS {
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int NEG_HI = ABS;
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int OP_SEL_0 = 4;
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int OP_SEL_1 = 8;
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int DST_OP_SEL = 8;
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}
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def DSTCLAMP {
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@ -1020,6 +1035,10 @@ class getSrcMod <ValueType VT> {
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);
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}
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class getOpSelMod <ValueType VT> {
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Operand ret = !if(!eq(VT.Value, f16.Value), FP16InputMods, IntOpSelMods);
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}
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// Return type of input modifiers operand specified input operand for DPP
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class getSrcModExt <ValueType VT> {
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bit isFP = !if(!eq(VT.Value, f16.Value), 1,
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@ -1133,6 +1152,37 @@ class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
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);
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}
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class getInsVOP3OpSel <RegisterOperand Src0RC,
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RegisterOperand Src1RC,
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RegisterOperand Src2RC,
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int NumSrcArgs,
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bit HasClamp,
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Operand Src0Mod,
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Operand Src1Mod,
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Operand Src2Mod> {
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dag ret = !if (!eq(NumSrcArgs, 2),
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!if (HasClamp,
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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clampmod:$clamp,
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op_sel:$op_sel),
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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op_sel:$op_sel)),
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// else NumSrcArgs == 3
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!if (HasClamp,
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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Src2Mod:$src2_modifiers, Src2RC:$src2,
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clampmod:$clamp,
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op_sel:$op_sel),
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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Src2Mod:$src2_modifiers, Src2RC:$src2,
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op_sel:$op_sel))
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);
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}
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class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
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bit HasModifiers, Operand Src0Mod, Operand Src1Mod> {
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@ -1279,6 +1329,34 @@ class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers,
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string ret = dst#", "#src0#src1#src2#"$op_sel$op_sel_hi"#mods#clamp;
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}
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class getAsmVOP3OpSel <int NumSrcArgs,
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bit HasClamp,
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bit Src0HasMods,
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bit Src1HasMods,
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bit Src2HasMods> {
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string dst = " $vdst";
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string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
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string isrc1 = !if(!eq(NumSrcArgs, 1), "",
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!if(!eq(NumSrcArgs, 2), " $src1",
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" $src1,"));
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string isrc2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
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string fsrc0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
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string fsrc1 = !if(!eq(NumSrcArgs, 1), "",
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!if(!eq(NumSrcArgs, 2), " $src1_modifiers",
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" $src1_modifiers,"));
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string fsrc2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
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string src0 = !if(Src0HasMods, fsrc0, isrc0);
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string src1 = !if(Src1HasMods, fsrc1, isrc1);
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string src2 = !if(Src2HasMods, fsrc2, isrc2);
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string clamp = !if(HasClamp, "$clamp", "");
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string ret = dst#", "#src0#src1#src2#"$op_sel"#clamp;
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}
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class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
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string dst = !if(HasDst,
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!if(!eq(DstVT.Size, 1),
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@ -1462,7 +1540,12 @@ class VOPProfile <list<ValueType> _ArgVT> {
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field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
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NumSrcArgs, HasClamp,
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Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
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field dag InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64,
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NumSrcArgs,
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HasClamp,
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getOpSelMod<Src0VT>.ret,
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getOpSelMod<Src1VT>.ret,
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getOpSelMod<Src2VT>.ret>.ret;
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field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs,
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HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
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field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
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@ -1473,6 +1556,11 @@ class VOPProfile <list<ValueType> _ArgVT> {
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field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
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field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, HasOMod, DstVT>.ret;
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field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasModifiers, HasClamp, DstVT>.ret;
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field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
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HasClamp,
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HasSrc0FloatMods,
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HasSrc1FloatMods,
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||||
HasSrc2FloatMods>.ret;
|
||||
field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
|
||||
field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
|
||||
field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
|
||||
@ -1495,6 +1583,8 @@ def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
|
||||
def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
|
||||
def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
|
||||
|
||||
def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
|
||||
|
||||
def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
|
||||
def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
|
||||
def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
|
||||
|
||||
@ -1288,12 +1288,32 @@ class FPMed3Pat<ValueType vt,
|
||||
(med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE, DSTOMOD.NONE)
|
||||
>;
|
||||
|
||||
class FP16Med3Pat<ValueType vt,
|
||||
Instruction med3Inst> : Pat<
|
||||
(fmaxnum (fminnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
|
||||
(VOP3Mods_nnan vt:$src1, i32:$src1_mods)),
|
||||
(fminnum_oneuse (fmaxnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods),
|
||||
(VOP3Mods_nnan vt:$src1, i32:$src1_mods)),
|
||||
(vt (VOP3Mods_nnan vt:$src2, i32:$src2_mods)))),
|
||||
(med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2, DSTCLAMP.NONE)
|
||||
>;
|
||||
|
||||
class Int16Med3Pat<Instruction med3Inst,
|
||||
SDPatternOperator max,
|
||||
SDPatternOperator max_oneuse,
|
||||
SDPatternOperator min_oneuse,
|
||||
ValueType vt = i32> : Pat<
|
||||
(max (min_oneuse vt:$src0, vt:$src1),
|
||||
(min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)),
|
||||
(med3Inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE)
|
||||
>;
|
||||
|
||||
def : FPMed3Pat<f32, V_MED3_F32>;
|
||||
|
||||
let Predicates = [isGFX9] in {
|
||||
def : FPMed3Pat<f16, V_MED3_F16>;
|
||||
def : IntMed3Pat<V_MED3_I16, smax, smax_oneuse, smin_oneuse, i16>;
|
||||
def : IntMed3Pat<V_MED3_U16, umax, umax_oneuse, umin_oneuse, i16>;
|
||||
def : FP16Med3Pat<f16, V_MED3_F16>;
|
||||
def : Int16Med3Pat<V_MED3_I16, smax, smax_oneuse, smin_oneuse, i16>;
|
||||
def : Int16Med3Pat<V_MED3_U16, umax, umax_oneuse, umin_oneuse, i16>;
|
||||
} // End Predicates = [isGFX9]
|
||||
|
||||
//============================================================================//
|
||||
|
||||
@ -53,6 +53,46 @@ class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
|
||||
ret1));
|
||||
}
|
||||
|
||||
class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
|
||||
list<dag> ret3 = [(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
|
||||
(VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
|
||||
(P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
|
||||
(P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
|
||||
|
||||
list<dag> ret2 = [(set P.DstVT:$vdst,
|
||||
(node !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
|
||||
(P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
|
||||
(P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
|
||||
|
||||
list<dag> ret1 = [(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
|
||||
|
||||
list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
|
||||
!if(!eq(P.NumSrcArgs, 2), ret2,
|
||||
ret1));
|
||||
}
|
||||
|
||||
class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
|
||||
list<dag> ret3 = [(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
|
||||
(VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
|
||||
(P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
|
||||
(P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
|
||||
|
||||
list<dag> ret2 = [(set P.DstVT:$vdst,
|
||||
(node !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
|
||||
(P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
|
||||
(P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
|
||||
|
||||
list<dag> ret1 = [(set P.DstVT:$vdst,
|
||||
(node (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
|
||||
|
||||
list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
|
||||
!if(!eq(P.NumSrcArgs, 2), ret2,
|
||||
ret1));
|
||||
}
|
||||
|
||||
class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
|
||||
list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
|
||||
list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
|
||||
@ -67,6 +107,16 @@ class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag,
|
||||
!if(P.HasModifiers, getVOP3ModPat<P, node>.ret, getVOP3Pat<P, node>.ret),
|
||||
VOP3Only>;
|
||||
|
||||
class VOP3OpSelInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
|
||||
VOP3_Pseudo<OpName, P,
|
||||
!if(isFloatType<P.Src0VT>.ret,
|
||||
getVOP3OpSelModPat<P, node>.ret,
|
||||
getVOP3OpSelPat<P, node>.ret),
|
||||
1, 0, 1> {
|
||||
|
||||
let AsmMatchConverter = "cvtVOP3OpSel";
|
||||
}
|
||||
|
||||
// Special case for v_div_fmas_{f32|f64}, since it seems to be the
|
||||
// only VOP instruction that implicitly reads VCC.
|
||||
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
|
||||
@ -93,6 +143,11 @@ class VOP3_Profile<VOPProfile P> : VOPProfile<P.ArgVT> {
|
||||
let Asm64 = " " # P.Asm64;
|
||||
}
|
||||
|
||||
class VOP3OpSel_Profile<VOPProfile P> : VOP3_Profile<P> {
|
||||
let HasClamp = 1;
|
||||
let HasOpSel = 1;
|
||||
}
|
||||
|
||||
class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
|
||||
// v_div_scale_{f32|f64} do not support input modifiers.
|
||||
let HasModifiers = 0;
|
||||
@ -303,7 +358,7 @@ defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
|
||||
} // End Predicates = [Has16BitInsts]
|
||||
|
||||
let SubtargetPredicate = isGFX9 in {
|
||||
def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16>>;
|
||||
def V_PACK_B32_F16 : VOP3OpSelInst <"v_pack_b32_f16", VOP3OpSel_Profile<VOP_B32_F16_F16>>;
|
||||
def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
|
||||
def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
|
||||
def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
|
||||
@ -313,17 +368,26 @@ def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
|
||||
|
||||
def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
|
||||
|
||||
def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmed3>;
|
||||
def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmed3>;
|
||||
def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUumed3>;
|
||||
def V_MED3_F16 : VOP3OpSelInst <"v_med3_f16", VOP3OpSel_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmed3>;
|
||||
def V_MED3_I16 : VOP3OpSelInst <"v_med3_i16", VOP3OpSel_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmed3>;
|
||||
def V_MED3_U16 : VOP3OpSelInst <"v_med3_u16", VOP3OpSel_Profile<VOP_I16_I16_I16_I16>, AMDGPUumed3>;
|
||||
|
||||
def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmin3>;
|
||||
def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmin3>;
|
||||
def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUumin3>;
|
||||
def V_MIN3_F16 : VOP3OpSelInst <"v_min3_f16", VOP3OpSel_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmin3>;
|
||||
def V_MIN3_I16 : VOP3OpSelInst <"v_min3_i16", VOP3OpSel_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmin3>;
|
||||
def V_MIN3_U16 : VOP3OpSelInst <"v_min3_u16", VOP3OpSel_Profile<VOP_I16_I16_I16_I16>, AMDGPUumin3>;
|
||||
|
||||
def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmax3>;
|
||||
def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmax3>;
|
||||
def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16>, AMDGPUumax3>;
|
||||
def V_MAX3_F16 : VOP3OpSelInst <"v_max3_f16", VOP3OpSel_Profile<VOP_F16_F16_F16_F16>, AMDGPUfmax3>;
|
||||
def V_MAX3_I16 : VOP3OpSelInst <"v_max3_i16", VOP3OpSel_Profile<VOP_I16_I16_I16_I16>, AMDGPUsmax3>;
|
||||
def V_MAX3_U16 : VOP3OpSelInst <"v_max3_u16", VOP3OpSel_Profile<VOP_I16_I16_I16_I16>, AMDGPUumax3>;
|
||||
|
||||
def V_ADD_I16 : VOP3OpSelInst <"v_add_i16", VOP3OpSel_Profile<VOP_I16_I16_I16>>;
|
||||
def V_SUB_I16 : VOP3OpSelInst <"v_sub_i16", VOP3OpSel_Profile<VOP_I16_I16_I16>>;
|
||||
|
||||
def V_MAD_U32_U16 : VOP3OpSelInst <"v_mad_u32_u16", VOP3OpSel_Profile<VOP_I32_I16_I16_I32>>;
|
||||
def V_MAD_I32_I16 : VOP3OpSelInst <"v_mad_i32_i16", VOP3OpSel_Profile<VOP_I32_I16_I16_I32>>;
|
||||
|
||||
def V_CVT_PKNORM_I16_F16 : VOP3OpSelInst <"v_cvt_pknorm_i16_f16", VOP3OpSel_Profile<VOP_B32_F16_F16>>;
|
||||
def V_CVT_PKNORM_U16_F16 : VOP3OpSelInst <"v_cvt_pknorm_u16_f16", VOP3OpSel_Profile<VOP_B32_F16_F16>>;
|
||||
} // End SubtargetPredicate = isGFX9
|
||||
|
||||
|
||||
@ -443,6 +507,11 @@ multiclass VOP3be_Real_vi<bits<10> op> {
|
||||
VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
|
||||
}
|
||||
|
||||
multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
|
||||
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
|
||||
VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
|
||||
}
|
||||
|
||||
} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
|
||||
|
||||
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
|
||||
@ -527,18 +596,27 @@ defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
|
||||
defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
|
||||
defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
|
||||
defm V_OR3_B32 : VOP3_Real_vi <0x202>;
|
||||
defm V_PACK_B32_F16 : VOP3_Real_vi <0x2a0>;
|
||||
defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
|
||||
|
||||
defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
|
||||
|
||||
defm V_MIN3_F16 : VOP3_Real_vi <0x1f4>;
|
||||
defm V_MIN3_I16 : VOP3_Real_vi <0x1f5>;
|
||||
defm V_MIN3_U16 : VOP3_Real_vi <0x1f6>;
|
||||
defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
|
||||
defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
|
||||
defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
|
||||
|
||||
defm V_MAX3_F16 : VOP3_Real_vi <0x1f7>;
|
||||
defm V_MAX3_I16 : VOP3_Real_vi <0x1f8>;
|
||||
defm V_MAX3_U16 : VOP3_Real_vi <0x1f9>;
|
||||
defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
|
||||
defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
|
||||
defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
|
||||
|
||||
defm V_MED3_F16 : VOP3_Real_vi <0x1fa>;
|
||||
defm V_MED3_I16 : VOP3_Real_vi <0x1fb>;
|
||||
defm V_MED3_U16 : VOP3_Real_vi <0x1fc>;
|
||||
defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
|
||||
defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
|
||||
defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
|
||||
|
||||
defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>;
|
||||
defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>;
|
||||
|
||||
defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
|
||||
defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
|
||||
|
||||
defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
|
||||
defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
|
||||
|
||||
@ -65,8 +65,13 @@ class VOP3Common <dag outs, dag ins, string asm = "",
|
||||
}
|
||||
|
||||
class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
|
||||
bit VOP3Only = 0, bit isVOP3P = 0> :
|
||||
InstSI <P.Outs64, !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64), "", pattern>,
|
||||
bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> :
|
||||
InstSI <P.Outs64,
|
||||
!if(isVop3OpSel,
|
||||
P.InsVOP3OpSel,
|
||||
!if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)),
|
||||
"",
|
||||
pattern>,
|
||||
VOP <opName>,
|
||||
SIMCInstr<opName#"_e64", SIEncodingFamily.NONE>,
|
||||
MnemonicAlias<opName#"_e64", opName> {
|
||||
@ -74,9 +79,12 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
|
||||
let isPseudo = 1;
|
||||
let isCodeGenOnly = 1;
|
||||
let UseNamedOperandTable = 1;
|
||||
let VOP3_OPSEL = isVop3OpSel;
|
||||
|
||||
string Mnemonic = opName;
|
||||
string AsmOperands = !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64);
|
||||
string AsmOperands = !if(isVop3OpSel,
|
||||
P.AsmVOP3OpSel,
|
||||
!if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
|
||||
|
||||
let Size = 8;
|
||||
let mayLoad = 0;
|
||||
@ -146,11 +154,11 @@ class VOP3P_Real<VOP3P_Pseudo ps, int EncodingFamily> :
|
||||
VOP3_Real<ps, EncodingFamily>;
|
||||
|
||||
class VOP3a<VOPProfile P> : Enc64 {
|
||||
bits<2> src0_modifiers;
|
||||
bits<4> src0_modifiers;
|
||||
bits<9> src0;
|
||||
bits<2> src1_modifiers;
|
||||
bits<3> src1_modifiers;
|
||||
bits<9> src1;
|
||||
bits<2> src2_modifiers;
|
||||
bits<3> src2_modifiers;
|
||||
bits<9> src2;
|
||||
bits<1> clamp;
|
||||
bits<2> omod;
|
||||
@ -189,6 +197,13 @@ class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
|
||||
let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
|
||||
}
|
||||
|
||||
class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
|
||||
let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
|
||||
let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
|
||||
let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
|
||||
let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
|
||||
}
|
||||
|
||||
class VOP3be <VOPProfile P> : Enc64 {
|
||||
bits<8> vdst;
|
||||
bits<2> src0_modifiers;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -31,6 +31,15 @@ v_pack_b32_f16 v1, v2, v3
|
||||
// GFX9: v_pack_b32_f16 v1, v2, v3 ; encoding: [0x01,0x00,0xa0,0xd2,0x02,0x07,0x02,0x00]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0]
|
||||
// GFX9: v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa0,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0]
|
||||
// GFX9: v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa0,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1]
|
||||
// GFX9: v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1] ; encoding: [0x05,0x40,0xa0,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_xad_u32 v1, v2, v3, v4
|
||||
// GFX9: v_xad_u32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf3,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
@ -51,10 +60,46 @@ v_max3_f16 v1, v2, v3, v4
|
||||
// GFX9: v_max3_f16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf7,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
|
||||
// GFX9: v_max3_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
|
||||
// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xf7,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
|
||||
// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0xf7,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
|
||||
// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0xf7,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
|
||||
// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf7,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
|
||||
// GFX9: v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_i16 v1, v2, v3, v4
|
||||
// GFX9: v_max3_i16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf8,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
|
||||
// GFX9: v_max3_i16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
|
||||
// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xf8,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
|
||||
// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0xf8,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
|
||||
// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0xf8,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
|
||||
// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf8,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
|
||||
// GFX9: v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf8,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_max3_u16 v1, v2, v3, v4
|
||||
// GFX9: v_max3_u16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xf9,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
@ -70,3 +115,78 @@ v_med3_i16 v1, v2, v3, v4
|
||||
v_med3_u16 v1, v2, v3, v4
|
||||
// GFX9: v_med3_u16 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xfc,0xd1,0x02,0x07,0x12,0x04]
|
||||
// NOVI: :1: error: instruction not supported on this GPU
|
||||
|
||||
v_mad_u32_u16 v5, v1, v2, v3
|
||||
// GFX9: v_mad_u32_u16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
|
||||
// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xf1,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
|
||||
// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0xf1,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
|
||||
// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0xf1,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
|
||||
// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf1,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
|
||||
// GFX9: v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xf1,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_i32_i16 v5, v1, v2, v3
|
||||
// GFX9: v_mad_i32_i16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
|
||||
// GFX9: v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0xf2,0xd1,0x01,0x05,0x0e,0x04]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, v1, v2
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, -v1, v2
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, -v1, v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x20]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, v1, -v2
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, v1, -v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x40]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, -v1, -v2
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, -v1, -v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x60]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, |v1|, v2
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, |v1|, v2 ; encoding: [0x05,0x01,0x99,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, v1, |v2|
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, v1, |v2| ; encoding: [0x05,0x02,0x99,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,0]
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0]
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0] ; encoding: [0x05,0x08,0x99,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1]
|
||||
// GFX9: v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x99,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_u16_f16 v5, -v1, -v2
|
||||
// GFX9: v_cvt_pknorm_u16_f16 v5, -v1, -v2 ; encoding: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x60]
|
||||
|
||||
v_cvt_pknorm_u16_f16 v5, |v1|, |v2|
|
||||
// GFX9: v_cvt_pknorm_u16_f16 v5, |v1|, |v2| ; encoding: [0x05,0x03,0x9a,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
|
||||
// GFX9: v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9a,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_add_i16 v5, v1, v2
|
||||
// GFX9: v_add_i16 v5, v1, v2 ; encoding: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_add_i16 v5, v1, v2 op_sel:[1,1,1]
|
||||
// GFX9: v_add_i16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9e,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_sub_i16 v5, v1, v2
|
||||
// GFX9: v_sub_i16 v5, v1, v2 ; encoding: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_sub_i16 v5, v1, v2 op_sel:[1,1,1]
|
||||
// GFX9: v_sub_i16 v5, v1, v2 op_sel:[1,1,1] ; encoding: [0x05,0x58,0x9f,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
v_sub_i16 v5, v1, v2 clamp
|
||||
// GFX9: v_sub_i16 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
|
||||
|
||||
@ -36,8 +36,8 @@ v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
|
||||
// GFX9: 35: error: failed parsing operand.
|
||||
v_pk_add_u16 v1, v2, v3 op_sel:[0,-1]
|
||||
|
||||
// GFX9: 40: error: not a valid operand.
|
||||
v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0]
|
||||
// GFX9: 42: error: not a valid operand.
|
||||
v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
|
||||
|
||||
// XXGFX9: invalid operand for instruction
|
||||
v_pk_add_u16 v1, v2, v3 neg_lo:[0,0]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user