diff --git a/lib/CodeGen/RegUsageInfoCollector.cpp b/lib/CodeGen/RegUsageInfoCollector.cpp
index f1c442ac38a..9db2af9f962 100644
--- a/lib/CodeGen/RegUsageInfoCollector.cpp
+++ b/lib/CodeGen/RegUsageInfoCollector.cpp
@@ -166,28 +166,27 @@ computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
   }
 
   // Insert any register fully saved via subregisters.
-  for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) {
-    if (SavedRegs.test(PReg))
-      continue;
+  for (const TargetRegisterClass *RC : TRI.regclasses()) {
+    if (!RC->CoveredBySubRegs)
+       continue;
 
-    // Check if PReg is fully covered by its subregs.
-    bool CoveredBySubRegs = false;
-    for (const TargetRegisterClass *RC : TRI.regclasses())
-      if (RC->CoveredBySubRegs && RC->contains(PReg)) {
-        CoveredBySubRegs = true;
-        break;
-      }
-    if (!CoveredBySubRegs)
-      continue;
+    for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) {
+      if (SavedRegs.test(PReg))
+        continue;
 
-    // Add PReg to SavedRegs if all subregs are saved.
-    bool AllSubRegsSaved = true;
-    for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR)
-      if (!SavedRegs.test(*SR)) {
-        AllSubRegsSaved = false;
-        break;
-      }
-    if (AllSubRegsSaved)
-      SavedRegs.set(PReg);
+      // Check if PReg is fully covered by its subregs.
+      if (!RC->contains(PReg))
+        continue;
+
+      // Add PReg to SavedRegs if all subregs are saved.
+      bool AllSubRegsSaved = true;
+      for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR)
+        if (!SavedRegs.test(*SR)) {
+          AllSubRegsSaved = false;
+          break;
+        }
+      if (AllSubRegsSaved)
+        SavedRegs.set(PReg);
+    }
   }
 }