Minor updates:

- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list

llvm-svn: 44627

CREDITS.TXT

@@ -257,3 +257,7 @@ W: http://web.mac.com/bwendling/
 D: Darwin exception handling
 D: MMX & SSSE3 instructions
 D: SPEC2006 support
+
+N: Scott Michel
+E: scottm@aero.org
+D: Added STI Cell SPU backend.

autoconf/configure.ac

@@ -363,8 +363,7 @@ AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
     [Build specific host targets: all,host-only,{target-name} (default=all)]),,
     enableval=all)
 case "$enableval" in
-  # Note: Add "CellSPU" to all when fully functional.
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips CellSPU" ;;
   host-only)
     case "$llvm_cv_target_arch" in
       x86)     TARGETS_TO_BUILD="X86" ;;

lib/Target/CellSPU/SPUCallingConv.td

@@ -48,7 +48,6 @@ def CC_SPU : CallingConv<[
   // The first 12 Vector arguments are passed in altivec registers.
   CCIfType<[v16i8, v8i16, v4i32, v4f32],
               CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
- */
 /*
   // Integer/FP values get stored in stack slots that are 8 bytes in size and
   // 8-byte aligned if there are no more registers to hold them.
@@ -56,6 +55,6 @@ def CC_SPU : CallingConv<[
   
   // Vectors get 16-byte stack slots that are 16-byte aligned.
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
-              CCAssignToStack<16, 16>>
+              CCAssignToStack<16, 16>>*/
 ]>;
  */