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R600/SI: Try to keep i32 mul on SALU
Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
This commit is contained in:
Matt Arsenault
parent
4e7d8af048
commit
a9af1cfd19
@ -908,6 +908,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
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case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
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case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
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case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
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case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
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case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
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case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
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@ -981,10 +982,14 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
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unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
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const TargetRegisterClass *RC = RI.getRegClass(RCID);
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unsigned Opcode = AMDGPU::V_MOV_B32_e32;
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if (MO.isReg()) {
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Opcode = AMDGPU::COPY;
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} else if (RI.isSGPRClass(RC)) {
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Opcode = AMDGPU::S_MOV_B32;
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} else if (MO.isImm()) {
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if (RC == &AMDGPU::VSrc_32RegClass)
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Opcode = AMDGPU::S_MOV_B32;
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}
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const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
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@ -274,11 +274,15 @@ def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
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[(set i64:$dst, (sra i64:$src0, i32:$src1))]
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>;
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} // End AddedComplexity = 1
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def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
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def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
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def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
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def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32",
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[(set i32:$dst, (mul i32:$src0, i32:$src1))]
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>;
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} // End AddedComplexity = 1
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def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
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def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
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def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
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@ -2499,11 +2503,6 @@ def : Pat <
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def : IMad24Pat<V_MAD_I32_I24>;
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def : UMad24Pat<V_MAD_U32_U24>;
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def : Pat <
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(mul i32:$src0, i32:$src1),
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(V_MUL_LO_I32 $src0, $src1)
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>;
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def : Pat <
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(mulhu i32:$src0, i32:$src1),
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(V_MUL_HI_U32 $src0, $src1)
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@ -2514,6 +2513,11 @@ def : Pat <
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(V_MUL_HI_I32 $src0, $src1)
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>;
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def : Pat <
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(mul i32:$src0, i32:$src1),
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(V_MUL_LO_I32 $src0, $src1)
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>;
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def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
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@ -7,8 +7,8 @@ target triple = "r600--"
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; FUNC-LABEL: @test
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; OPT: mul nsw i32
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; OPT-NEXT: sext
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; SI-LLC: V_MUL_LO_I32
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; SI-LLC-NOT: V_MUL_HI
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; SI-LLC: S_MUL_I32
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; SI-LLC-NOT: MUL
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define void @test(i8 addrspace(1)* nocapture readonly %in, i32 %a, i8 %b) {
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entry:
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%0 = mul nsw i32 %a, 3
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@ -3,14 +3,14 @@
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; mul24 and mad24 are affected
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; FUNC-LABEL: @test2
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; FUNC-LABEL: @test_mul_v2i32
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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define void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1) * %in
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%b = load <2 x i32> addrspace(1) * %b_ptr
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@ -19,7 +19,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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ret void
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}
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; FUNC-LABEL: @test4
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; FUNC-LABEL: @v_mul_v4i32
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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@ -30,7 +30,7 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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define void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1) * %in
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%b = load <4 x i32> addrspace(1) * %b_ptr
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@ -39,12 +39,26 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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ret void
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}
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; FUNC-LABEL: @trunc_i64_mul_to_i32
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; FUNC-LABEL: @s_trunc_i64_mul_to_i32
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; SI: S_LOAD_DWORD
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; SI: S_LOAD_DWORD
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; SI: S_MUL_I32
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; SI: BUFFER_STORE_DWORD
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define void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%mul = mul i64 %b, %a
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%trunc = trunc i64 %mul to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @v_trunc_i64_mul_to_i32
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; SI: S_LOAD_DWORD
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; SI: S_LOAD_DWORD
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; SI: V_MUL_LO_I32
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; SI: BUFFER_STORE_DWORD
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define void @trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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define void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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%a = load i64 addrspace(1)* %aptr, align 8
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%b = load i64 addrspace(1)* %bptr, align 8
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%mul = mul i64 %b, %a
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%trunc = trunc i64 %mul to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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@ -56,7 +70,7 @@ define void @trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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; FUNC-LABEL: @mul64_sext_c
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; EG-DAG: MULLO_INT
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; EG-DAG: MULHI_INT
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; SI-DAG: V_MUL_LO_I32
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; SI-DAG: S_MUL_I32
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; SI-DAG: V_MUL_HI_I32
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define void @mul64_sext_c(i64 addrspace(1)* %out, i32 %in) {
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entry:
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@ -66,16 +80,120 @@ entry:
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ret void
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}
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; FUNC-LABEL: @v_mul64_sext_c:
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; EG-DAG: MULLO_INT
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; EG-DAG: MULHI_INT
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; SI-DAG: V_MUL_LO_I32
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; SI-DAG: V_MUL_HI_I32
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; SI: S_ENDPGM
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define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%val = load i32 addrspace(1)* %in, align 4
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%ext = sext i32 %val to i64
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%mul = mul i64 %ext, 80
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @v_mul64_sext_inline_imm:
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; SI-DAG: V_MUL_LO_I32 v{{[0-9]+}}, 9, v{{[0-9]+}}
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; SI-DAG: V_MUL_HI_I32 v{{[0-9]+}}, 9, v{{[0-9]+}}
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; SI: S_ENDPGM
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define void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%val = load i32 addrspace(1)* %in, align 4
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%ext = sext i32 %val to i64
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%mul = mul i64 %ext, 9
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @s_mul_i32:
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; SI: S_LOAD_DWORD [[SRC0:s[0-9]+]],
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; SI: S_LOAD_DWORD [[SRC1:s[0-9]+]],
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; SI: S_MUL_I32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
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; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: BUFFER_STORE_DWORD [[VRESULT]],
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; SI: S_ENDPGM
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define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%mul = mul i32 %a, %b
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store i32 %mul, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_mul_i32
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; SI: V_MUL_LO_I32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%a = load i32 addrspace(1)* %in
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%b = load i32 addrspace(1)* %b_ptr
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%result = mul i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; A standard 64-bit multiply. The expansion should be around 6 instructions.
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; It would be difficult to match the expansion correctly without writing
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; a really complicated list of FileCheck expressions. I don't want
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; to confuse people who may 'break' this test with a correct optimization,
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; so this test just uses FUNC-LABEL to make sure the compiler does not
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; crash with a 'failed to select' error.
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; FUNC-LABEL: @mul64
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define void @mul64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%0 = mul i64 %a, %b
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store i64 %0, i64 addrspace(1)* %out
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; FUNC-LABEL: @s_mul_i64:
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define void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%mul = mul i64 %a, %b
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @v_mul_i64
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; SI: V_MUL_LO_I32
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define void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
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%a = load i64 addrspace(1)* %aptr, align 8
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%b = load i64 addrspace(1)* %bptr, align 8
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%mul = mul i64 %a, %b
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @mul32_in_branch
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; SI: V_MUL_LO_I32
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define void @mul32_in_branch(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i32 addrspace(1)* %in
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br label %endif
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else:
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%2 = mul i32 %a, %b
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @mul64_in_branch
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; SI-DAG: V_MUL_LO_I32
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; SI-DAG: V_MUL_HI_U32
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; SI: S_ENDPGM
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define void @mul64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i64 addrspace(1)* %in
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br label %endif
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else:
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%2 = mul i64 %a, %b
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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@ -10,10 +10,10 @@ define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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ret void
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}
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; SI-LABEL: @test:
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; SI: V_ASHR
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; SI-LABEL: @test_s_sext_i32_to_i64:
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; SI: S_ASHR_I32
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; SI: S_ENDPG
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define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
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define void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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%mul = mul i32 %a, %b
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%add = add i32 %mul, %c
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