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Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction.
llvm-svn: 57246
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@ -2891,11 +2891,11 @@ let AddedComplexity = 15 in {
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
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(MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
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(MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
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(MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
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(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
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(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
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(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
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(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
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}
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// Splat v2f64 / v2i64
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22
test/CodeGen/X86/2008-10-07-SSEISelBug.ll
Normal file
22
test/CodeGen/X86/2008-10-07-SSEISelBug.ll
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@ -0,0 +1,22 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2
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define <4 x float> @f(float %w) nounwind {
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entry:
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%retval = alloca <4 x float> ; <<4 x float>*> [#uses=2]
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%w.addr = alloca float ; <float*> [#uses=2]
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%.compoundliteral = alloca <4 x float> ; <<4 x float>*> [#uses=2]
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store float %w, float* %w.addr
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%tmp = load float* %w.addr ; <float> [#uses=1]
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%0 = insertelement <4 x float> undef, float %tmp, i32 0 ; <<4 x float>> [#uses=1]
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%1 = insertelement <4 x float> %0, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
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%2 = insertelement <4 x float> %1, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
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%3 = insertelement <4 x float> %2, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
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store <4 x float> %3, <4 x float>* %.compoundliteral
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%tmp1 = load <4 x float>* %.compoundliteral ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp1, <4 x float>* %retval
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br label %return
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return: ; preds = %entry
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%4 = load <4 x float>* %retval ; <<4 x float>> [#uses=1]
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ret <4 x float> %4
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}
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