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Change this code ot pass register classes into the stack slot spiller/reloader

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code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.

llvm-svn: 23536
This commit is contained in:
Chris Lattner 2005-09-30 01:29:00 +00:00
parent ec85d13393
commit a9cd99bbc1
4 changed files with 19 additions and 11 deletions
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6
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -200,7 +200,8 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
MachineBasicBlock::iterator I = MBB->begin();
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
// Insert the spill to the stack frame.
RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
0 /*FIXME*/);
}
// Add code to restore the callee-save registers in each exiting block.
@ -225,7 +226,8 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
// Restore all registers immediately before the return and any terminators
// that preceed it.
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
0 /*FIXME*/);
assert(I != MBB->begin() &&
"loadRegFromStackSlot didn't insert any code!");
// Insert in reverse order. loadRegFromStackSlot can insert multiple

4
lib/CodeGen/RegAllocLocal.cpp
View File

@ -270,7 +270,7 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
++NumStores; // Update statistics
}
@ -476,7 +476,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
<< RegInfo->getName(PhysReg) << "\n");
// Add move instruction(s)
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;

4
lib/CodeGen/RegAllocSimple.cpp
View File

@ -135,7 +135,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s)
++NumLoads;
RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
@ -147,7 +147,7 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s)
++NumStores;
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
}

16
lib/CodeGen/VirtRegMap.cpp
View File

@ -163,18 +163,20 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF,
unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
const TargetRegisterClass* RC =
MF.getSSARegMap()->getRegClass(VirtReg);
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII));
}
if (MO.isDef()) {
MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
++NumStores;
}
}
@ -386,6 +388,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
// Otherwise, reload it and remember that we have it.
PhysReg = VRM.getPhys(VirtReg);
const TargetRegisterClass* RC =
MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
RecheckRegister:
// Note that, if we reused a register for a previous operand, the
@ -406,7 +410,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
// was used. This isn't good because it means we have
// to undo a previous reuse.
MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
Op.StackSlot);
Op.StackSlot, RC);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable);
@ -431,7 +435,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
}
ContinueReload:
PhysRegsUsed[PhysReg] = true;
MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
// This invalidates PhysReg.
ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
@ -553,6 +557,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
if (!TakenCareOf) {
// The only vregs left are stack slot definitions.
int StackSlot = VRM.getStackSlot(VirtReg);
const TargetRegisterClass *RC =
MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
unsigned PhysReg;
// If this is a def&use operand, and we used a different physreg for
@ -564,7 +570,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
PhysReg = MO.getReg();
PhysRegsUsed[PhysReg] = true;
MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DEBUG(std::cerr << "Store:\t" << *next(MII));
MI.SetMachineOperandReg(i, PhysReg);