RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

[X86] Remove duplicate lines from scheduler models. NFC

Browse Source 
llvm-svn: 322615
This commit is contained in:
Craig Topper 2018-01-17 03:50:21 +00:00
parent 26f42ee3dd
commit aa7c3ff71e
4 changed files with 0 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86SchedBroadwell.td
View File

@ -3827,7 +3827,6 @@ def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPor
let ResourceCycles = [2,2,8,1,10,2,39]; let ResourceCycles = [2,2,8,1,10,2,39];
} }
def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>; def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> { def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
let Latency = 63; let Latency = 63;
@ -3863,7 +3862,6 @@ def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,
let ResourceCycles = [9,9,11,8,1,11,21,30]; let ResourceCycles = [9,9,11,8,1,11,21,30];
} }
def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>; def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
} // SchedModel } // SchedModel

2
lib/Target/X86/X86SchedHaswell.td
View File

@ -4249,7 +4249,6 @@ def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPor
let ResourceCycles = [2,2,8,1,10,2,39]; let ResourceCycles = [2,2,8,1,10,2,39];
} }
def: InstRW<[HWWriteResGroup177], (instregex "FLDENVm")>; def: InstRW<[HWWriteResGroup177], (instregex "FLDENVm")>;
def: InstRW<[HWWriteResGroup177], (instregex "FLDENVm")>;
def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
let Latency = 64; let Latency = 64;
@ -4292,7 +4291,6 @@ def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,
let ResourceCycles = [9,9,11,8,1,11,21,30]; let ResourceCycles = [9,9,11,8,1,11,21,30];
} }
def: InstRW<[HWWriteResGroup183], (instregex "FSTENVm")>; def: InstRW<[HWWriteResGroup183], (instregex "FSTENVm")>;
def: InstRW<[HWWriteResGroup183], (instregex "FSTENVm")>;
def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> { def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> {
let Latency = 26; let Latency = 26;

2
lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -3945,7 +3945,6 @@ def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,
let ResourceCycles = [2,8,5,10,39]; let ResourceCycles = [2,8,5,10,39];
} }
def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>; def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;
def: InstRW<[SKLWriteResGroup217], (instregex "FLDENVm")>;
def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 63; let Latency = 63;
@ -3988,6 +3987,5 @@ def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKL
let ResourceCycles = [9,1,11,16,1,11,21,30]; let ResourceCycles = [9,1,11,16,1,11,21,30];
} }
def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>; def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;
def: InstRW<[SKLWriteResGroup223], (instregex "FSTENVm")>;
} // SchedModel } // SchedModel

2
lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -6432,7 +6432,6 @@ def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,
let ResourceCycles = [2,8,5,10,39]; let ResourceCycles = [2,8,5,10,39];
} }
def: InstRW<[SKXWriteResGroup258], (instregex "FLDENVm")>; def: InstRW<[SKXWriteResGroup258], (instregex "FLDENVm")>;
def: InstRW<[SKXWriteResGroup258], (instregex "FLDENVm")>;
def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
let Latency = 63; let Latency = 63;
@ -6489,7 +6488,6 @@ def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKX
let ResourceCycles = [9,1,11,16,1,11,21,30]; let ResourceCycles = [9,1,11,16,1,11,21,30];
} }
def: InstRW<[SKXWriteResGroup266], (instregex "FSTENVm")>; def: InstRW<[SKXWriteResGroup266], (instregex "FSTENVm")>;
def: InstRW<[SKXWriteResGroup266], (instregex "FSTENVm")>;
def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> { def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 140; let Latency = 140;