From aa9082cd092bddbbc850669f50968a976842451d Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 17 Jan 2019 10:11:59 +0000 Subject: [PATCH] Fix capitalization. NFC llvm-svn: 351425 --- lib/Target/ARM/ARMCallLowering.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/Target/ARM/ARMCallLowering.cpp b/lib/Target/ARM/ARMCallLowering.cpp index a64544c20d1..aba0863e02b 100644 --- a/lib/Target/ARM/ARMCallLowering.cpp +++ b/lib/Target/ARM/ARMCallLowering.cpp @@ -540,19 +540,19 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, // Create the call instruction so we can add the implicit uses of arg // registers, but don't insert it yet. - bool isDirect = !Callee.isReg(); - auto CallOpcode = getCallOpcode(STI, isDirect); + bool IsDirect = !Callee.isReg(); + auto CallOpcode = getCallOpcode(STI, IsDirect); auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); - bool isThumb = STI.isThumb(); - if (isThumb) + bool IsThumb = STI.isThumb(); + if (IsThumb) MIB.add(predOps(ARMCC::AL)); MIB.add(Callee); - if (!isDirect) { + if (!IsDirect) { auto CalleeReg = Callee.getReg(); if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) { - unsigned CalleeIdx = isThumb ? 2 : 0; + unsigned CalleeIdx = IsThumb ? 2 : 0; MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(), *MIB.getInstr(), MIB->getDesc(), Callee, CalleeIdx));