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[AArch64][GlobalISel] Select @llvm.aarch64.ldxr.* intrinsics
Same thing as D66897, but for ldxr.* instead. Add a GISelPredicateCode to the ldxr_* definitions, which allows us to import them. Add select-ldxr-intrin.mir, and update arm64-ldxr-stxr.ll. Differential Revision: https://reviews.llvm.org/D66898 llvm-svn: 370378
This commit is contained in:
Jessica Paquette
parent
7a3c720e33
commit
aac0d557f1
@ -204,19 +204,27 @@ def : Pat<(relaxed_store<atomic_store_64>
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def ldxr_1 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 1); }];
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}
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def ldxr_2 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 2); }];
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}
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def ldxr_4 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 4); }];
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}
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def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 8); }];
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}
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def : Pat<(ldxr_1 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
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95
test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
Normal file
95
test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
Normal file
@ -0,0 +1,95 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_load_i8(i8* %addr) { ret void }
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define void @test_load_i16(i16* %addr) { ret void }
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define void @test_load_i32(i32* %addr) { ret void }
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define void @test_load_i64(i64* %addr) { ret void }
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...
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---
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name: test_load_i8
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i8
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load 1 from %ir.addr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_32
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; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 1 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: test_load_i16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i16
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load 2 from %ir.addr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_32
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; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 2 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: test_load_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load 4 from %ir.addr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_32
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; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 4 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: test_load_i64
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i64
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load 8 from %ir.addr)
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; CHECK: $x1 = COPY [[LDXRX]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 8 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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@ -33,6 +33,7 @@ declare i32 @llvm.aarch64.stxp(i64, i64, i8*) nounwind
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@var = global i64 0, align 8
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; FALLBACK-NOT: remark:{{.*}}test_load_i8
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define void @test_load_i8(i8* %addr) {
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; CHECK-LABEL: test_load_i8:
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; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
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@ -40,6 +41,12 @@ define void @test_load_i8(i8* %addr) {
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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; FIXME: GlobalISel doesn't fold ands/adds into load/store addressing modes
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; right now/ So, we won't get the :lo12:var.
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; GISEL-LABEL: test_load_i8:
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; GISEL: ldxrb w[[LOADVAL:[0-9]+]], [x0]
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; GISEL-NOT: uxtb
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; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
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%val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
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%shortval = trunc i64 %val to i8
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%extval = zext i8 %shortval to i64
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@ -47,6 +54,7 @@ define void @test_load_i8(i8* %addr) {
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ret void
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}
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; FALLBACK-NOT: remark:{{.*}}test_load_i16
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define void @test_load_i16(i16* %addr) {
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; CHECK-LABEL: test_load_i16:
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; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
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@ -54,6 +62,10 @@ define void @test_load_i16(i16* %addr) {
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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; GISEL-LABEL: test_load_i16:
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; GISEL: ldxrh w[[LOADVAL:[0-9]+]], [x0]
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; GISEL-NOT: uxtb
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; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
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%val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
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%shortval = trunc i64 %val to i16
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%extval = zext i16 %shortval to i64
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@ -61,6 +73,7 @@ define void @test_load_i16(i16* %addr) {
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ret void
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}
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; FALLBACK-NOT: remark:{{.*}}test_load_i32
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define void @test_load_i32(i32* %addr) {
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; CHECK-LABEL: test_load_i32:
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; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
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@ -68,6 +81,10 @@ define void @test_load_i32(i32* %addr) {
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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; GISEL-LABEL: test_load_i32:
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; GISEL: ldxr w[[LOADVAL:[0-9]+]], [x0]
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; GISEL-NOT: uxtb
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; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
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%val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
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%shortval = trunc i64 %val to i32
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%extval = zext i32 %shortval to i64
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@ -75,11 +92,16 @@ define void @test_load_i32(i32* %addr) {
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ret void
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}
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; FALLBACK-NOT: remark:{{.*}}test_load_i64
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define void @test_load_i64(i64* %addr) {
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; CHECK-LABEL: test_load_i64:
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; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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; GISEL-LABEL: test_load_i64:
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; GISEL: ldxr x[[LOADVAL:[0-9]+]], [x0]
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; GISEL-NOT: uxtb
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; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
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%val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
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store i64 %val, i64* @var, align 8
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ret void
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