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[Hexagon] NFC. Canonicalizing absolute address instruction names.
llvm-svn: 283507
This commit is contained in:
Colin LeMahieu
parent
3ccb460d6b
commit
aad216e2a8
@ -417,46 +417,46 @@ void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI,
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// GP relative instruction in the absence of the corresponding immediate
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// extender.
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switch (MCI.getOpcode()) {
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case Hexagon::S2_storerbabs:
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case Hexagon::PS_storerbabs:
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opcode = Hexagon::S2_storerbgp;
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break;
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case Hexagon::S2_storerhabs:
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case Hexagon::PS_storerhabs:
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opcode = Hexagon::S2_storerhgp;
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break;
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case Hexagon::S2_storerfabs:
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case Hexagon::PS_storerfabs:
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opcode = Hexagon::S2_storerfgp;
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break;
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case Hexagon::S2_storeriabs:
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case Hexagon::PS_storeriabs:
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opcode = Hexagon::S2_storerigp;
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break;
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case Hexagon::S2_storerbnewabs:
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case Hexagon::PS_storerbnewabs:
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opcode = Hexagon::S2_storerbnewgp;
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break;
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case Hexagon::S2_storerhnewabs:
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case Hexagon::PS_storerhnewabs:
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opcode = Hexagon::S2_storerhnewgp;
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break;
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case Hexagon::S2_storerinewabs:
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case Hexagon::PS_storerinewabs:
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opcode = Hexagon::S2_storerinewgp;
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break;
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case Hexagon::S2_storerdabs:
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case Hexagon::PS_storerdabs:
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opcode = Hexagon::S2_storerdgp;
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break;
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case Hexagon::L4_loadrb_abs:
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case Hexagon::PS_loadrbabs:
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opcode = Hexagon::L2_loadrbgp;
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break;
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case Hexagon::L4_loadrub_abs:
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case Hexagon::PS_loadrubabs:
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opcode = Hexagon::L2_loadrubgp;
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break;
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case Hexagon::L4_loadrh_abs:
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case Hexagon::PS_loadrhabs:
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opcode = Hexagon::L2_loadrhgp;
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break;
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case Hexagon::L4_loadruh_abs:
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case Hexagon::PS_loadruhabs:
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opcode = Hexagon::L2_loadruhgp;
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break;
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case Hexagon::L4_loadri_abs:
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case Hexagon::PS_loadriabs:
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opcode = Hexagon::L2_loadrigp;
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break;
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case Hexagon::L4_loadrd_abs:
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case Hexagon::PS_loadrdabs:
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opcode = Hexagon::L2_loadrdgp;
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break;
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default:
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@ -811,20 +811,20 @@ static const unsigned int StoreConditionalOpcodeData[][2] = {
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// HexagonII::INST_ICLASS_LD
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// HexagonII::INST_ICLASS_LD_ST_2
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static unsigned int LoadStoreOpcodeData[][2] = {{L4_loadrd_abs, 0x49c00000},
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{L4_loadri_abs, 0x49800000},
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{L4_loadruh_abs, 0x49600000},
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{L4_loadrh_abs, 0x49400000},
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{L4_loadrub_abs, 0x49200000},
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{L4_loadrb_abs, 0x49000000},
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{S2_storerdabs, 0x48c00000},
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{S2_storerinewabs, 0x48a01000},
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{S2_storerhnewabs, 0x48a00800},
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{S2_storerbnewabs, 0x48a00000},
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{S2_storeriabs, 0x48800000},
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{S2_storerfabs, 0x48600000},
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{S2_storerhabs, 0x48400000},
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{S2_storerbabs, 0x48000000}};
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static unsigned int LoadStoreOpcodeData[][2] = {{PS_loadrdabs, 0x49c00000},
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{PS_loadriabs, 0x49800000},
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{PS_loadruhabs, 0x49600000},
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{PS_loadrhabs, 0x49400000},
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{PS_loadrubabs, 0x49200000},
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{PS_loadrbabs, 0x49000000},
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{PS_storerdabs, 0x48c00000},
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{PS_storerinewabs, 0x48a01000},
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{PS_storerhnewabs, 0x48a00800},
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{PS_storerbnewabs, 0x48a00000},
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{PS_storeriabs, 0x48800000},
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{PS_storerfabs, 0x48600000},
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{PS_storerhabs, 0x48400000},
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{PS_storerbabs, 0x48000000}};
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static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData);
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static const size_t NumLS = array_lengthof(LoadStoreOpcodeData);
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@ -982,15 +982,15 @@ static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {
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break;
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// op: g16_2
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case (Hexagon::L4_loadri_abs):
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case (Hexagon::PS_loadriabs):
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++shift;
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// op: g16_1
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case Hexagon::L4_loadrh_abs:
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case Hexagon::L4_loadruh_abs:
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case Hexagon::PS_loadrhabs:
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case Hexagon::PS_loadruhabs:
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++shift;
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// op: g16_0
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case Hexagon::L4_loadrb_abs:
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case Hexagon::L4_loadrub_abs: {
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case Hexagon::PS_loadrbabs:
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case Hexagon::PS_loadrubabs: {
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// op: Rd
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Value |= insn & UINT64_C(31);
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DecodeIntRegsRegisterClass(MI, Value, 0, 0);
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@ -1001,7 +1001,7 @@ static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {
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break;
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}
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case Hexagon::L4_loadrd_abs: {
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case Hexagon::PS_loadrdabs: {
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Value = insn & UINT64_C(31);
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DecodeDoubleRegsRegisterClass(MI, Value, 0, 0);
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Value = (insn >> 11) & UINT64_C(49152);
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@ -1011,7 +1011,7 @@ static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {
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break;
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}
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case Hexagon::S2_storerdabs: {
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case Hexagon::PS_storerdabs: {
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// op: g16_3
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Value = (insn >> 11) & UINT64_C(49152);
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Value |= (insn >> 7) & UINT64_C(15872);
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@ -1025,13 +1025,13 @@ static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {
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}
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// op: g16_2
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case Hexagon::S2_storerinewabs:
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case Hexagon::PS_storerinewabs:
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++shift;
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// op: g16_1
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case Hexagon::S2_storerhnewabs:
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case Hexagon::PS_storerhnewabs:
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++shift;
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// op: g16_0
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case Hexagon::S2_storerbnewabs: {
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case Hexagon::PS_storerbnewabs: {
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Value = (insn >> 11) & UINT64_C(49152);
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Value |= (insn >> 7) & UINT64_C(15872);
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Value |= (insn >> 5) & UINT64_C(256);
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@ -1044,14 +1044,14 @@ static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) {
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}
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// op: g16_2
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case Hexagon::S2_storeriabs:
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case Hexagon::PS_storeriabs:
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++shift;
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// op: g16_1
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case Hexagon::S2_storerhabs:
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case Hexagon::S2_storerfabs:
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case Hexagon::PS_storerhabs:
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case Hexagon::PS_storerfabs:
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++shift;
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// op: g16_0
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case Hexagon::S2_storerbabs: {
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case Hexagon::PS_storerbabs: {
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Value = (insn >> 11) & UINT64_C(49152);
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Value |= (insn >> 7) & UINT64_C(15872);
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Value |= (insn >> 5) & UINT64_C(256);
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@ -999,7 +999,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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case L2_loadrb_pci:
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case L2_loadrb_pcr:
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case L2_loadrb_pi:
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case L4_loadrb_abs:
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case PS_loadrbabs:
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case L4_loadrb_ap:
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case L4_loadrb_rr:
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case L4_loadrb_ur:
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@ -1013,7 +1013,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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case L2_loadrub_pci:
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case L2_loadrub_pcr:
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case L2_loadrub_pi:
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case L4_loadrub_abs:
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case PS_loadrubabs:
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case L4_loadrub_ap:
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case L4_loadrub_rr:
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case L4_loadrub_ur:
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@ -1027,7 +1027,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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case L2_loadrh_pci:
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case L2_loadrh_pcr:
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case L2_loadrh_pi:
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case L4_loadrh_abs:
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case PS_loadrhabs:
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case L4_loadrh_ap:
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case L4_loadrh_rr:
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case L4_loadrh_ur:
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@ -1042,7 +1042,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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case L2_loadruh_pcr:
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case L2_loadruh_pi:
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case L4_loadruh_rr:
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case L4_loadruh_abs:
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case PS_loadruhabs:
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case L4_loadruh_ap:
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case L4_loadruh_ur:
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BitNum = 16;
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@ -1056,7 +1056,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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case L2_loadri_pcr:
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case L2_loadri_pi:
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case L2_loadw_locked:
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case L4_loadri_abs:
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case PS_loadriabs:
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case L4_loadri_ap:
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case L4_loadri_rr:
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case L4_loadri_ur:
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@ -1072,7 +1072,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
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case L2_loadrd_pcr:
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case L2_loadrd_pi:
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case L4_loadd_locked:
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case L4_loadrd_abs:
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case PS_loadrdabs:
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case L4_loadrd_ap:
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case L4_loadrd_rr:
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case L4_loadrd_ur:
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@ -3534,7 +3534,7 @@ multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
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Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 0, isPredicable = 1 in
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def S2_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
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def PS_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
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// Predicated
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def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
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@ -3636,7 +3636,7 @@ multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
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bits<2> MajOp> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 0, isPredicable = 1 in
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def S2_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
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def PS_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
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// Predicated
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def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
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@ -3733,14 +3733,14 @@ class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
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(MI Addr:$addr, (ValueMod Value:$val))>;
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let AddedComplexity = 30 in {
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def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
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def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
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def: Storea_pat<store, I32, addrga, S2_storeriabs>;
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def: Storea_pat<store, I64, addrga, S2_storerdabs>;
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def: Storea_pat<truncstorei8, I32, addrga, PS_storerbabs>;
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def: Storea_pat<truncstorei16, I32, addrga, PS_storerhabs>;
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def: Storea_pat<store, I32, addrga, PS_storeriabs>;
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def: Storea_pat<store, I64, addrga, PS_storerdabs>;
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def: Stoream_pat<truncstorei8, I64, addrga, LoReg, S2_storerbabs>;
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def: Stoream_pat<truncstorei16, I64, addrga, LoReg, S2_storerhabs>;
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def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
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def: Stoream_pat<truncstorei8, I64, addrga, LoReg, PS_storerbabs>;
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def: Stoream_pat<truncstorei16, I64, addrga, LoReg, PS_storerhabs>;
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def: Stoream_pat<truncstorei32, I64, addrga, LoReg, PS_storeriabs>;
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}
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def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
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@ -3856,7 +3856,7 @@ multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
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Operand ImmOp, bits<3> MajOp> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
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let opExtendable = 1, isPredicable = 1 in
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def L4_#NAME#_abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
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def PS_#NAME#abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
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// Predicated
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defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
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@ -3885,20 +3885,20 @@ class LoadAbs_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
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(VT (MI tglobaladdr:$absaddr))>;
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let AddedComplexity = 30 in {
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def: LoadAbs_pats <load, L4_loadri_abs>;
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def: LoadAbs_pats <zextloadi1, L4_loadrub_abs>;
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def: LoadAbs_pats <sextloadi8, L4_loadrb_abs>;
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def: LoadAbs_pats <extloadi8, L4_loadrub_abs>;
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def: LoadAbs_pats <zextloadi8, L4_loadrub_abs>;
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def: LoadAbs_pats <sextloadi16, L4_loadrh_abs>;
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def: LoadAbs_pats <extloadi16, L4_loadruh_abs>;
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def: LoadAbs_pats <zextloadi16, L4_loadruh_abs>;
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def: LoadAbs_pats <load, L4_loadrd_abs, i64>;
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def: LoadAbs_pats <load, PS_loadriabs>;
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def: LoadAbs_pats <zextloadi1, PS_loadrubabs>;
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def: LoadAbs_pats <sextloadi8, PS_loadrbabs>;
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def: LoadAbs_pats <extloadi8, PS_loadrubabs>;
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def: LoadAbs_pats <zextloadi8, PS_loadrubabs>;
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def: LoadAbs_pats <sextloadi16, PS_loadrhabs>;
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def: LoadAbs_pats <extloadi16, PS_loadruhabs>;
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def: LoadAbs_pats <zextloadi16, PS_loadruhabs>;
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def: LoadAbs_pats <load, PS_loadrdabs, i64>;
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}
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let AddedComplexity = 30 in
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def: Pat<(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$absaddr))),
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(Zext64 (L4_loadrub_abs tglobaladdr:$absaddr))>;
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(Zext64 (PS_loadrubabs tglobaladdr:$absaddr))>;
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//===----------------------------------------------------------------------===//
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// multiclass for load instructions with GP-relative addressing mode.
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@ -3936,10 +3936,10 @@ def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
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def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
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// Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
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def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
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def: Loadam_pat<load, i1, addrga, I32toI1, PS_loadrubabs>;
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def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
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def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
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def: Stoream_pat<store, I1, addrga, I1toI32, PS_storerbabs>;
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def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
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// Map from load(globaladdress) -> mem[u][bhwd](#foo)
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@ -3972,17 +3972,17 @@ def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
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def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
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let AddedComplexity = 30 in {
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def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
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def: Storea_pat<truncstorei16, I32, u32ImmPred, S2_storerhabs>;
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def: Storea_pat<store, I32, u32ImmPred, S2_storeriabs>;
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def: Storea_pat<truncstorei8, I32, u32ImmPred, PS_storerbabs>;
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def: Storea_pat<truncstorei16, I32, u32ImmPred, PS_storerhabs>;
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def: Storea_pat<store, I32, u32ImmPred, PS_storeriabs>;
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}
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let AddedComplexity = 30 in {
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def: Loada_pat<load, i32, u32ImmPred, L4_loadri_abs>;
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def: Loada_pat<sextloadi8, i32, u32ImmPred, L4_loadrb_abs>;
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def: Loada_pat<zextloadi8, i32, u32ImmPred, L4_loadrub_abs>;
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def: Loada_pat<sextloadi16, i32, u32ImmPred, L4_loadrh_abs>;
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def: Loada_pat<zextloadi16, i32, u32ImmPred, L4_loadruh_abs>;
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def: Loada_pat<load, i32, u32ImmPred, PS_loadriabs>;
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def: Loada_pat<sextloadi8, i32, u32ImmPred, PS_loadrbabs>;
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def: Loada_pat<zextloadi8, i32, u32ImmPred, PS_loadrubabs>;
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def: Loada_pat<sextloadi16, i32, u32ImmPred, PS_loadrhabs>;
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def: Loada_pat<zextloadi16, i32, u32ImmPred, PS_loadruhabs>;
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}
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// Indexed store word - global address.
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@ -3992,74 +3992,74 @@ defm: Storex_add_pat<store, addrga, u6_2ImmPred, S4_storeiri_io>;
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// Load from a global address that has only one use in the current basic block.
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let AddedComplexity = 100 in {
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def: Loada_pat<extloadi8, i32, addrga, L4_loadrub_abs>;
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def: Loada_pat<sextloadi8, i32, addrga, L4_loadrb_abs>;
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def: Loada_pat<zextloadi8, i32, addrga, L4_loadrub_abs>;
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def: Loada_pat<extloadi8, i32, addrga, PS_loadrubabs>;
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def: Loada_pat<sextloadi8, i32, addrga, PS_loadrbabs>;
|
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def: Loada_pat<zextloadi8, i32, addrga, PS_loadrubabs>;
|
||||
|
||||
def: Loada_pat<extloadi16, i32, addrga, L4_loadruh_abs>;
|
||||
def: Loada_pat<sextloadi16, i32, addrga, L4_loadrh_abs>;
|
||||
def: Loada_pat<zextloadi16, i32, addrga, L4_loadruh_abs>;
|
||||
def: Loada_pat<extloadi16, i32, addrga, PS_loadruhabs>;
|
||||
def: Loada_pat<sextloadi16, i32, addrga, PS_loadrhabs>;
|
||||
def: Loada_pat<zextloadi16, i32, addrga, PS_loadruhabs>;
|
||||
|
||||
def: Loada_pat<load, i32, addrga, L4_loadri_abs>;
|
||||
def: Loada_pat<load, i64, addrga, L4_loadrd_abs>;
|
||||
def: Loada_pat<load, i32, addrga, PS_loadriabs>;
|
||||
def: Loada_pat<load, i64, addrga, PS_loadrdabs>;
|
||||
}
|
||||
|
||||
// Store to a global address that has only one use in the current basic block.
|
||||
let AddedComplexity = 100 in {
|
||||
def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
|
||||
def: Storea_pat<store, I32, addrga, S2_storeriabs>;
|
||||
def: Storea_pat<store, I64, addrga, S2_storerdabs>;
|
||||
def: Storea_pat<truncstorei8, I32, addrga, PS_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, addrga, PS_storerhabs>;
|
||||
def: Storea_pat<store, I32, addrga, PS_storeriabs>;
|
||||
def: Storea_pat<store, I64, addrga, PS_storerdabs>;
|
||||
|
||||
def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
|
||||
def: Stoream_pat<truncstorei32, I64, addrga, LoReg, PS_storeriabs>;
|
||||
}
|
||||
|
||||
// i8/i16/i32 -> i64 loads
|
||||
// We need a complexity of 120 here to override preceding handling of
|
||||
// zextload.
|
||||
let AddedComplexity = 120 in {
|
||||
def: Loadam_pat<extloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
|
||||
def: Loadam_pat<sextloadi8, i64, addrga, Sext64, L4_loadrb_abs>;
|
||||
def: Loadam_pat<zextloadi8, i64, addrga, Zext64, L4_loadrub_abs>;
|
||||
def: Loadam_pat<extloadi8, i64, addrga, Zext64, PS_loadrubabs>;
|
||||
def: Loadam_pat<sextloadi8, i64, addrga, Sext64, PS_loadrbabs>;
|
||||
def: Loadam_pat<zextloadi8, i64, addrga, Zext64, PS_loadrubabs>;
|
||||
|
||||
def: Loadam_pat<extloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
|
||||
def: Loadam_pat<sextloadi16, i64, addrga, Sext64, L4_loadrh_abs>;
|
||||
def: Loadam_pat<zextloadi16, i64, addrga, Zext64, L4_loadruh_abs>;
|
||||
def: Loadam_pat<extloadi16, i64, addrga, Zext64, PS_loadruhabs>;
|
||||
def: Loadam_pat<sextloadi16, i64, addrga, Sext64, PS_loadrhabs>;
|
||||
def: Loadam_pat<zextloadi16, i64, addrga, Zext64, PS_loadruhabs>;
|
||||
|
||||
def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
|
||||
def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
|
||||
def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
|
||||
def: Loadam_pat<extloadi32, i64, addrga, Zext64, PS_loadriabs>;
|
||||
def: Loadam_pat<sextloadi32, i64, addrga, Sext64, PS_loadriabs>;
|
||||
def: Loadam_pat<zextloadi32, i64, addrga, Zext64, PS_loadriabs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100 in {
|
||||
def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
|
||||
def: Loada_pat<sextloadi8, i32, addrgp, L4_loadrb_abs>;
|
||||
def: Loada_pat<zextloadi8, i32, addrgp, L4_loadrub_abs>;
|
||||
def: Loada_pat<extloadi8, i32, addrgp, PS_loadrubabs>;
|
||||
def: Loada_pat<sextloadi8, i32, addrgp, PS_loadrbabs>;
|
||||
def: Loada_pat<zextloadi8, i32, addrgp, PS_loadrubabs>;
|
||||
|
||||
def: Loada_pat<extloadi16, i32, addrgp, L4_loadruh_abs>;
|
||||
def: Loada_pat<sextloadi16, i32, addrgp, L4_loadrh_abs>;
|
||||
def: Loada_pat<zextloadi16, i32, addrgp, L4_loadruh_abs>;
|
||||
def: Loada_pat<extloadi16, i32, addrgp, PS_loadruhabs>;
|
||||
def: Loada_pat<sextloadi16, i32, addrgp, PS_loadrhabs>;
|
||||
def: Loada_pat<zextloadi16, i32, addrgp, PS_loadruhabs>;
|
||||
|
||||
def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
|
||||
def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
|
||||
def: Loada_pat<load, i32, addrgp, PS_loadriabs>;
|
||||
def: Loada_pat<load, i64, addrgp, PS_loadrdabs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100 in {
|
||||
def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
|
||||
def: Storea_pat<store, I32, addrgp, S2_storeriabs>;
|
||||
def: Storea_pat<store, I64, addrgp, S2_storerdabs>;
|
||||
def: Storea_pat<truncstorei8, I32, addrgp, PS_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, addrgp, PS_storerhabs>;
|
||||
def: Storea_pat<store, I32, addrgp, PS_storeriabs>;
|
||||
def: Storea_pat<store, I64, addrgp, PS_storerdabs>;
|
||||
}
|
||||
|
||||
def: Loada_pat<atomic_load_8, i32, addrgp, L4_loadrub_abs>;
|
||||
def: Loada_pat<atomic_load_16, i32, addrgp, L4_loadruh_abs>;
|
||||
def: Loada_pat<atomic_load_32, i32, addrgp, L4_loadri_abs>;
|
||||
def: Loada_pat<atomic_load_64, i64, addrgp, L4_loadrd_abs>;
|
||||
def: Loada_pat<atomic_load_8, i32, addrgp, PS_loadrubabs>;
|
||||
def: Loada_pat<atomic_load_16, i32, addrgp, PS_loadruhabs>;
|
||||
def: Loada_pat<atomic_load_32, i32, addrgp, PS_loadriabs>;
|
||||
def: Loada_pat<atomic_load_64, i64, addrgp, PS_loadrdabs>;
|
||||
|
||||
def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, PS_storerbabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, PS_storerhabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, PS_storeriabs>;
|
||||
def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, PS_storerdabs>;
|
||||
|
||||
let Constraints = "@earlyclobber $dst" in
|
||||
def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
|
||||
|
||||
@ -118,9 +118,9 @@ let AddedComplexity = 20 in {
|
||||
}
|
||||
|
||||
let AddedComplexity = 80 in {
|
||||
def: Loada_pat<load, f32, u32ImmPred, L4_loadri_abs>;
|
||||
def: Loada_pat<load, f32, addrga, L4_loadri_abs>;
|
||||
def: Loada_pat<load, f64, addrga, L4_loadrd_abs>;
|
||||
def: Loada_pat<load, f32, u32ImmPred, PS_loadriabs>;
|
||||
def: Loada_pat<load, f32, addrga, PS_loadriabs>;
|
||||
def: Loada_pat<load, f64, addrga, PS_loadrdabs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100 in {
|
||||
@ -153,8 +153,8 @@ let AddedComplexity = 20 in {
|
||||
}
|
||||
|
||||
let AddedComplexity = 80 in {
|
||||
def: Storea_pat<store, F32, addrga, S2_storeriabs>;
|
||||
def: Storea_pat<store, F64, addrga, S2_storerdabs>;
|
||||
def: Storea_pat<store, F32, addrga, PS_storeriabs>;
|
||||
def: Storea_pat<store, F64, addrga, PS_storerdabs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100 in {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user