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[DAGCombine] Fix issue with out of bound constant rotation (PR33828)

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Take the modulo of rotations by a constant greater than or equal to the bit-width

llvm-svn: 308302
This commit is contained in:
Simon Pilgrim 2017-07-18 12:31:46 +00:00
parent d4e97a7afd
commit aada93f97c
2 changed files with 58 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -5279,11 +5279,21 @@ SDValue DAGCombiner::visitRotate(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
unsigned Bitsize = VT.getScalarSizeInBits();
// fold (rot x, 0) -> x
if (isNullConstantOrNullSplatConstant(N1))
return N0;
// fold (rot x, c) -> (rot x, c % BitSize)
if (ConstantSDNode *Cst = isConstOrConstSplat(N1)) {
if (Cst->getAPIntValue().uge(Bitsize)) {
uint64_t RotAmt = Cst->getAPIntValue().urem(Bitsize);
return DAG.getNode(N->getOpcode(), dl, VT, N0,
DAG.getConstant(RotAmt, dl, N1.getValueType()));
}
}
// fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
if (N1.getOpcode() == ISD::TRUNCATE &&
N1.getOperand(0).getOpcode() == ISD::AND) {
@ -5302,7 +5312,6 @@ SDValue DAGCombiner::visitRotate(SDNode *N) {
unsigned CombineOp = SameSide ? ISD::ADD : ISD::SUB;
if (SDValue CombinedShift =
DAG.FoldConstantArithmetic(CombineOp, dl, ShiftVT, C1, C2)) {
unsigned Bitsize = VT.getScalarSizeInBits();
SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT);
SDValue CombinedShiftNorm = DAG.FoldConstantArithmetic(
ISD::SREM, dl, ShiftVT, CombinedShift.getNode(),

48
test/CodeGen/X86/pr33828.ll Normal file
View File

@ -0,0 +1,48 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=X64
@var_580 = external local_unnamed_addr global i8, align 1
define void @foo() {
; X86-LABEL: foo:
; X86: # BB#0: # %entry
; X86-NEXT: movsbl var_580, %eax
; X86-NEXT: testl $-536870913, %eax # imm = 0xDFFFFFFF
; X86-NEXT: jne .LBB0_1
; X86-NEXT: # BB#2: # %if.end13
; X86-NEXT: retl
; X86-NEXT: .LBB0_1: # %if.then11
;
; X64-LABEL: foo:
; X64: # BB#0: # %entry
; X64-NEXT: movsbl {{.*}}(%rip), %eax
; X64-NEXT: testl $-536870913, %eax # imm = 0xDFFFFFFF
; X64-NEXT: jne .LBB0_1
; X64-NEXT: # BB#2: # %if.end13
; X64-NEXT: retq
; X64-NEXT: .LBB0_1: # %if.then11
entry:
%tmp = icmp ugt i8 undef, 60
%phitmp = zext i1 %tmp to i16
br label %if.end
if.end:
%tmp1 = load i8, i8* @var_580, align 1
%conv7 = sext i8 %tmp1 to i32
%conv8 = zext i16 %phitmp to i32
%mul = shl nuw nsw i32 %conv8, 1
%div9 = udiv i32 %mul, 71
%sub = add nsw i32 %div9, -3
%shl = shl i32 1, %sub
%neg = xor i32 %shl, -1
%and = and i32 %neg, %conv7
%tobool10 = icmp eq i32 %and, 0
br i1 %tobool10, label %if.end13, label %if.then11
if.then11:
unreachable
if.end13:
ret void
}