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Fix encoding of Thumb1 LDRB and STRB.

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llvm-svn: 121581
This commit is contained in:
Owen Anderson 2010-12-10 22:11:13 +00:00
parent d7f424dec3
commit aaf97da84b
3 changed files with 18 additions and 0 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -191,6 +191,8 @@ namespace {
const { return 0; }
unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getTAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)

1
lib/Target/ARM/ARMInstrThumb.td
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@ -103,6 +103,7 @@ def MemModeThumbAsmOperand : AsmOperandClass {
//
def t_addrmode_rr : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
let EncoderMethod = "getTAddrModeRegRegOpValue";
let PrintMethod = "printThumbAddrModeRROperand";
let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
}

15
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -129,6 +129,10 @@ public:
uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
/// operand.
uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
@ -504,6 +508,17 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
Fixups);
}
/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
uint32_t ARMMCCodeEmitter::
getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO1 = MI.getOperand(OpIdx);
const MCOperand &MO2 = MI.getOperand(OpIdx+1);
unsigned Rn = getARMRegisterNumbering(MO1.getReg());
unsigned Rm = getARMRegisterNumbering(MO2.getReg());
return (Rm << 3) | Rn;
}
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
uint32_t ARMMCCodeEmitter::
getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,