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https://github.com/RPCS3/llvm-mirror.git
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[AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.
llvm-svn: 198193
This commit is contained in:
Hao Liu
parent
8bef865160
commit
ab32d54fad
@ -418,10 +418,8 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else {
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assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
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RC->hasType(MVT::f128))
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&& "Expected integer or floating type for store");
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} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
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RC->hasType(MVT::f128)) {
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switch (RC->getSize()) {
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case 4: StoreOp = AArch64::LSFP32_STR; break;
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case 8: StoreOp = AArch64::LSFP64_STR; break;
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@ -429,6 +427,22 @@ AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else { // The spill of D tuples is implemented by Q tuples
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if (RC == &AArch64::QPairRegClass)
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StoreOp = AArch64::ST1x2_16B;
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else if (RC == &AArch64::QTripleRegClass)
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StoreOp = AArch64::ST1x3_16B;
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else if (RC == &AArch64::QQuadRegClass)
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StoreOp = AArch64::ST1x4_16B;
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else
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llvm_unreachable("Unknown reg class");
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MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
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// Vector store has different operands from other store instructions.
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NewMI.addFrameIndex(FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO);
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return;
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}
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MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
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@ -464,10 +478,8 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else {
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assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64)
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|| RC->hasType(MVT::f128))
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&& "Expected integer or floating type for store");
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} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
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RC->hasType(MVT::f128)) {
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switch (RC->getSize()) {
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case 4: LoadOp = AArch64::LSFP32_LDR; break;
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case 8: LoadOp = AArch64::LSFP64_LDR; break;
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@ -475,6 +487,21 @@ AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else { // The spill of D tuples is implemented by Q tuples
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if (RC == &AArch64::QPairRegClass)
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LoadOp = AArch64::LD1x2_16B;
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else if (RC == &AArch64::QTripleRegClass)
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LoadOp = AArch64::LD1x3_16B;
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else if (RC == &AArch64::QQuadRegClass)
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LoadOp = AArch64::LD1x4_16B;
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else
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llvm_unreachable("Unknown reg class");
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MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
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// Vector load has different operands from other load instructions.
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NewMI.addFrameIndex(FrameIdx)
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.addMemOperand(MMO);
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return;
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}
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MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
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@ -572,6 +599,21 @@ void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
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MinOffset = -0x40 * AccessScale;
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MaxOffset = 0x3f * AccessScale;
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return;
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case AArch64::LD1x2_16B: case AArch64::ST1x2_16B:
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AccessScale = 32;
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MinOffset = 0;
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MaxOffset = 0xfff * AccessScale;
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return;
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case AArch64::LD1x3_16B: case AArch64::ST1x3_16B:
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AccessScale = 48;
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MinOffset = 0;
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MaxOffset = 0xfff * AccessScale;
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return;
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case AArch64::LD1x4_16B: case AArch64::ST1x4_16B:
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AccessScale = 64;
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MinOffset = 0;
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MaxOffset = 0xfff * AccessScale;
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return;
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}
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}
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@ -76,6 +76,12 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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return Reserved;
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}
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static bool hasFrameOffset(int opcode) {
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return opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B &&
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opcode != AArch64::LD1x4_16B && opcode != AArch64::ST1x2_16B &&
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opcode != AArch64::ST1x3_16B && opcode != AArch64::ST1x4_16B;
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}
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void
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AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
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int SPAdj,
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@ -110,8 +116,10 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
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int64_t Offset;
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Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
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IsCalleeSaveOp);
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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// A vector load/store instruction doesn't have an offset operand.
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bool HasOffsetOp = hasFrameOffset(MI.getOpcode());
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if (HasOffsetOp)
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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// DBG_VALUE instructions have no real restrictions so they can be handled
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// easily.
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@ -124,7 +132,7 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
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const AArch64InstrInfo &TII =
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*static_cast<const AArch64InstrInfo*>(MF.getTarget().getInstrInfo());
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int MinOffset, MaxOffset, OffsetScale;
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if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s) {
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if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s || !HasOffsetOp) {
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MinOffset = 0;
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MaxOffset = 0xfff;
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OffsetScale = 1;
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@ -133,10 +141,12 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
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TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
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}
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// The frame lowering has told us a base and offset it thinks we should use to
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// access this variable, but it's still up to us to make sure the values are
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// legal for the instruction in question.
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if (Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) {
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// There are two situations we don't use frame + offset directly in the
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// instruction:
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// (1) The offset can't really be scaled
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// (2) Can't encode offset as it doesn't have an offset operand
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if ((Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) ||
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(!HasOffsetOp && Offset != 0)) {
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unsigned BaseReg =
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MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
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emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
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@ -150,7 +160,8 @@ AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
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assert(Offset >= 0 && "Unexpected negative offset from SP");
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale);
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if (HasOffsetOp)
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale);
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}
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unsigned
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134
test/CodeGen/AArch64/neon-vector-list-spill.ll
Normal file
134
test/CodeGen/AArch64/neon-vector-list-spill.ll
Normal file
@ -0,0 +1,134 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast
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; FIXME: We should not generate ld/st for such register spill/fill, because the
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; test case seems very simple and the register pressure is not high. If the
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; spill/fill algorithm is optimized, this test case may not be triggered. And
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; then we can delete it.
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define i32 @spill.DPairReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DPairReg:
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; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <2 x i32>, <2 x i32> } %vld, 0
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%res = extractelement <2 x i32> %vld.extract, i32 1
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ret i32 %res
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}
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define i16 @spill.DTripleReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DTripleReg:
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; CHECK: ld3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %vld, 0
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%res = extractelement <4 x i16> %vld.extract, i32 1
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ret i16 %res
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}
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define i16 @spill.DQuadReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DQuadReg:
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; CHECK: ld4 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %vld, 0
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%res = extractelement <4 x i16> %vld.extract, i32 0
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ret i16 %res
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}
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define i32 @spill.QPairReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QPairReg:
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; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0
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%res = extractelement <4 x i32> %vld.extract, i32 1
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ret i32 %res
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}
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define float @spill.QTripleReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QTripleReg:
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; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld3.extract = extractvalue { <4 x float>, <4 x float>, <4 x float> } %vld3, 0
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%res = extractelement <4 x float> %vld3.extract, i32 1
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ret float %res
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}
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define i8 @spill.QQuadReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QQuadReg:
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; CHECK: ld4 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld, 0
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%res = extractelement <16 x i8> %vld.extract, i32 1
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ret i8 %res
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}
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declare { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8*, i32)
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declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8*, i32)
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declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16(i8*, i32)
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declare { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32(i8*, i32)
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declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32(i8*, i32)
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8*, i32)
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declare void @foo()
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