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[RISCV] Remove unneeded !eq comparing a single bit value to 0/1 in RISCVInstrInfoVPseudos.td. NFC

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Instead we can either use the bit directly. If it was checking for
0 we need to swap the operands or use !not.
This commit is contained in:
Craig Topper 2020-12-22 11:40:51 -08:00
parent 213a4b317b
commit ab5054f7c8
1 changed files with 23 additions and 23 deletions
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46
lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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@ -543,7 +543,7 @@ class VPseudoBinaryCarryIn<VReg RetClass,
bit CarryIn, bit CarryIn,
string Constraint> : string Constraint> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
!if(!eq(CarryIn, 1), !if(CarryIn,
(ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, GPR:$vl, (ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, GPR:$vl,
ixlenimm:$sew), ixlenimm:$sew),
(ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew)), []>, (ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew)), []>,
@ -554,8 +554,8 @@ class VPseudoBinaryCarryIn<VReg RetClass,
let usesCustomInserter = 1; let usesCustomInserter = 1;
let Constraints = Constraint; let Constraints = Constraint;
let Uses = [VL, VTYPE]; let Uses = [VL, VTYPE];
let VLIndex = !if(!eq(CarryIn, 1), 4, 3); let VLIndex = !if(CarryIn, 4, 3);
let SEWIndex = !if(!eq(CarryIn, 1), 5, 4); let SEWIndex = !if(CarryIn, 5, 4);
let MergeOpIndex = InvalidIndex.V; let MergeOpIndex = InvalidIndex.V;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
let VLMul = MInfo.value; let VLMul = MInfo.value;
@ -675,8 +675,8 @@ multiclass VPseudoBinaryV_VV {
multiclass VPseudoBinaryV_VX<bit IsFloat> { multiclass VPseudoBinaryV_VX<bit IsFloat> {
foreach m = MxList.m in foreach m = MxList.m in
defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.vrclass, m.vrclass, defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.vrclass, m.vrclass,
!if(!eq(IsFloat, 0), GPR, FPR32), m>; !if(IsFloat, FPR32, GPR), m>;
} }
multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> { multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> {
@ -699,8 +699,8 @@ multiclass VPseudoBinaryW_VV {
multiclass VPseudoBinaryW_VX<bit IsFloat> { multiclass VPseudoBinaryW_VX<bit IsFloat> {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.wvrclass, m.vrclass, defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.wvrclass, m.vrclass,
!if(!eq(IsFloat, 0), GPR, FPR32), m, !if(IsFloat, FPR32, GPR), m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
@ -712,8 +712,8 @@ multiclass VPseudoBinaryW_WV {
multiclass VPseudoBinaryW_WX<bit IsFloat> { multiclass VPseudoBinaryW_WX<bit IsFloat> {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm !if(!eq(IsFloat, 0), "_WX", "_WF") : VPseudoBinary<m.wvrclass, m.wvrclass, defm !if(IsFloat, "_WF", "_WX") : VPseudoBinary<m.wvrclass, m.wvrclass,
!if(!eq(IsFloat, 0), GPR, FPR32), m, !if(IsFloat, FPR32, GPR), m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
@ -741,9 +741,9 @@ multiclass VPseudoBinaryV_WI {
multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1, multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> { string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
def "_VV" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX : def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR, VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)), !if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)), GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, m.vrclass, m, CarryIn, Constraint>; m.vrclass, m.vrclass, m, CarryIn, Constraint>;
} }
@ -751,9 +751,9 @@ multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1, multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> { string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
def "_VX" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX : def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR, VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)), !if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)), GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, GPR, m, CarryIn, Constraint>; m.vrclass, GPR, m, CarryIn, Constraint>;
} }
@ -761,9 +761,9 @@ multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1, multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> { string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
def "_VI" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX : def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR, VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)), !if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)), GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, simm5, m, CarryIn, Constraint>; m.vrclass, simm5, m, CarryIn, Constraint>;
} }
@ -789,8 +789,8 @@ multiclass VPseudoBinaryM_VV {
multiclass VPseudoBinaryM_VX<bit IsFloat> { multiclass VPseudoBinaryM_VX<bit IsFloat> {
foreach m = MxList.m in foreach m = MxList.m in
defm !if(!eq(IsFloat, 0), "_VX", "_VF") : defm !if(IsFloat, "_VF", "_VX") :
VPseudoBinary<VR, m.vrclass, !if(!eq(IsFloat, 0), GPR, FPR32), m, VPseudoBinary<VR, m.vrclass, !if(IsFloat, FPR32, GPR), m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
@ -1374,7 +1374,7 @@ multiclass VPatBinaryV_VM<string intrinsic, string instruction,
bit CarryOut = 0> { bit CarryOut = 0> {
foreach vti = AllIntegerVectors in foreach vti = AllIntegerVectors in
defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM", defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",
!if(!eq(CarryOut, 1), vti.Mask, vti.Vector), !if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Mask,
vti.SEW, vti.LMul, vti.SEW, vti.LMul,
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
@ -1384,7 +1384,7 @@ multiclass VPatBinaryV_XM<string intrinsic, string instruction,
bit CarryOut = 0> { bit CarryOut = 0> {
foreach vti = AllIntegerVectors in foreach vti = AllIntegerVectors in
defm : VPatBinaryCarryIn<intrinsic, instruction, "VXM", defm : VPatBinaryCarryIn<intrinsic, instruction, "VXM",
!if(!eq(CarryOut, 1), vti.Mask, vti.Vector), !if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, XLenVT, vti.Mask, vti.Vector, XLenVT, vti.Mask,
vti.SEW, vti.LMul, vti.SEW, vti.LMul,
vti.RegClass, GPR>; vti.RegClass, GPR>;
@ -1394,7 +1394,7 @@ multiclass VPatBinaryV_IM<string intrinsic, string instruction,
bit CarryOut = 0> { bit CarryOut = 0> {
foreach vti = AllIntegerVectors in foreach vti = AllIntegerVectors in
defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM", defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM",
!if(!eq(CarryOut, 1), vti.Mask, vti.Vector), !if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, XLenVT, vti.Mask, vti.Vector, XLenVT, vti.Mask,
vti.SEW, vti.LMul, vti.SEW, vti.LMul,
vti.RegClass, simm5>; vti.RegClass, simm5>;