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[X86] Make isel select the 2-byte register form of INC/DEC even in non-64-bit mode. Convert to the 1-byte form in non-64-bit mode as part of MCInst lowering.
Overall this seems simpler. It reduces duplication of patterns between both modes and it simplifies the memory folding/unfolding tables as they don't need to create fake instructions just to keep track of 64-bitness. llvm-svn: 225252
This commit is contained in:
Craig Topper
parent
b0f02c8870
commit
ab5fd9d585
@ -2370,19 +2370,16 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
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unsigned ResultReg = 0;
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// Check if we have an immediate version.
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if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
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static const unsigned Opc[2][2][4] = {
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{ { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r },
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{ X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r } },
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{ { X86::INC8r, X86::INC64_16r, X86::INC64_32r, X86::INC64r },
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{ X86::DEC8r, X86::DEC64_16r, X86::DEC64_32r, X86::DEC64r } }
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static const unsigned Opc[2][4] = {
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{ X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r },
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{ X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r }
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};
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if (BaseOpc == X86ISD::INC || BaseOpc == X86ISD::DEC) {
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ResultReg = createResultReg(TLI.getRegClassFor(VT));
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bool Is64Bit = Subtarget->is64Bit();
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bool IsDec = BaseOpc == X86ISD::DEC;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(Opc[Is64Bit][IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
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TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill));
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} else
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ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill,
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@ -456,33 +456,29 @@ def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
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"inc{b}\t$dst",
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[(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))],
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IIC_UNARY_REG>;
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let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
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def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
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"inc{w}\t$dst", [], IIC_UNARY_REG>,
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OpSize16, Requires<[Not64BitMode]>;
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def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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"inc{l}\t$dst", [], IIC_UNARY_REG>,
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OpSize32, Requires<[Not64BitMode]>;
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let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
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def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
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"inc{w}\t$dst",
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[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
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IIC_UNARY_REG>, OpSize16;
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def INC32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
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"inc{l}\t$dst",
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[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
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IIC_UNARY_REG>, OpSize32;
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def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
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[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
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IIC_UNARY_REG>;
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} // isConvertibleToThreeAddress = 1, CodeSize = 1
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// In 64-bit mode, single byte INC and DEC cannot be encoded.
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let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
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// Can transform into LEA.
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def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
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"inc{w}\t$dst", [], IIC_UNARY_REG>, OpSize16;
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def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
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"inc{l}\t$dst", [], IIC_UNARY_REG>, OpSize32;
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def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
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"dec{w}\t$dst", [], IIC_UNARY_REG>, OpSize16;
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def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
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"dec{l}\t$dst", [], IIC_UNARY_REG>, OpSize32;
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} // isConvertibleToThreeAddress = 1, CodeSize = 2
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// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
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let CodeSize = 1, hasSideEffects = 0 in {
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def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
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"inc{w}\t$dst", [], IIC_UNARY_REG>,
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OpSize16, Requires<[Not64BitMode]>;
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def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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"inc{l}\t$dst", [], IIC_UNARY_REG>,
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OpSize32, Requires<[Not64BitMode]>;
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} // CodeSize = 1, hasSideEffects = 0
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} // Constraints = "$src1 = $dst", SchedRW
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let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
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@ -491,35 +487,13 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
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(implicit EFLAGS)], IIC_UNARY_MEM>;
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def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
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[(store (add (loadi16 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize16, Requires<[Not64BitMode]>;
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(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
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def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
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[(store (add (loadi32 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize32, Requires<[Not64BitMode]>;
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(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
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def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
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[(store (add (loadi64 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>;
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// These are duplicates of their 32-bit counterparts. Only needed so X86 knows
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// how to unfold them.
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// FIXME: What is this for??
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def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
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[(store (add (loadi16 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize16, Requires<[In64BitMode]>;
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def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
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[(store (add (loadi32 addr:$dst), 1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize32, Requires<[In64BitMode]>;
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def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
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[(store (add (loadi16 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize16, Requires<[In64BitMode]>;
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def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
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[(store (add (loadi32 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize32, Requires<[In64BitMode]>;
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} // CodeSize = 2, SchedRW
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let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
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@ -528,17 +502,29 @@ def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
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"dec{b}\t$dst",
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[(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))],
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IIC_UNARY_REG>;
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let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
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def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
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"dec{w}\t$dst", [], IIC_UNARY_REG>,
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OpSize16, Requires<[Not64BitMode]>;
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def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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"dec{l}\t$dst", [], IIC_UNARY_REG>,
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OpSize32, Requires<[Not64BitMode]>;
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let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
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def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
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"dec{w}\t$dst",
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[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
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IIC_UNARY_REG>, OpSize16;
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def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
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"dec{l}\t$dst",
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[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
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IIC_UNARY_REG>, OpSize32;
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def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
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[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
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IIC_UNARY_REG>;
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} // CodeSize = 2
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} // isConvertibleToThreeAddress = 1, CodeSize = 2
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// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
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let CodeSize = 1, hasSideEffects = 0 in {
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def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
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"dec{w}\t$dst", [], IIC_UNARY_REG>,
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OpSize16, Requires<[Not64BitMode]>;
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def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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"dec{l}\t$dst", [], IIC_UNARY_REG>,
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OpSize32, Requires<[Not64BitMode]>;
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} // CodeSize = 1, hasSideEffects = 0
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} // Constraints = "$src1 = $dst", SchedRW
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@ -548,32 +534,16 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
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(implicit EFLAGS)], IIC_UNARY_MEM>;
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def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
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[(store (add (loadi16 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize16, Requires<[Not64BitMode]>;
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(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
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def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
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[(store (add (loadi32 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>,
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OpSize32, Requires<[Not64BitMode]>;
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(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
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def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
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[(store (add (loadi64 addr:$dst), -1), addr:$dst),
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(implicit EFLAGS)], IIC_UNARY_MEM>;
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} // CodeSize = 2, SchedRW
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} // Defs = [EFLAGS]
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let Predicates = [Not64BitMode] in {
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def : Pat<(X86inc_flag GR16:$src1), (INC16r GR16:$src1)>;
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def : Pat<(X86inc_flag GR32:$src1), (INC32r GR32:$src1)>;
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def : Pat<(X86dec_flag GR16:$src1), (DEC16r GR16:$src1)>;
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def : Pat<(X86dec_flag GR32:$src1), (DEC32r GR32:$src1)>;
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}
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let Predicates = [In64BitMode] in {
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def : Pat<(X86inc_flag GR16:$src1), (INC64_16r GR16:$src1)>;
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def : Pat<(X86inc_flag GR32:$src1), (INC64_32r GR32:$src1)>;
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def : Pat<(X86dec_flag GR16:$src1), (DEC64_16r GR16:$src1)>;
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def : Pat<(X86dec_flag GR32:$src1), (DEC64_32r GR32:$src1)>;
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}
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/// X86TypeInfo - This is a bunch of information that describes relevant X86
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/// information about value types. For example, it can tell you what the
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/// register class and preferred load to use.
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@ -1724,35 +1724,18 @@ def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
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def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
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(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
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// Increment reg.
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// Do not make INC if it is slow
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def : Pat<(add GR8:$src, 1),
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(INC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
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def : Pat<(add GR16:$src, 1),
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(INC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
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def : Pat<(add GR16:$src, 1),
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(INC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
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def : Pat<(add GR32:$src, 1),
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(INC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
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def : Pat<(add GR32:$src, 1),
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(INC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
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def : Pat<(add GR64:$src, 1),
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(INC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
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// Decrement reg.
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// Do not make DEC if it is slow
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def : Pat<(add GR8:$src, -1),
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(DEC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
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def : Pat<(add GR16:$src, -1),
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(DEC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
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def : Pat<(add GR16:$src, -1),
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(DEC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
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def : Pat<(add GR32:$src, -1),
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(DEC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
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def : Pat<(add GR32:$src, -1),
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(DEC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
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def : Pat<(add GR64:$src, -1),
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(DEC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
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// Increment/Decrement reg.
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// Do not make INC/DEC if it is slow
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let Predicates = [NotSlowIncDec] in {
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def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
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def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
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def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
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def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
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def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
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def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
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def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
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def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
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}
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// or reg/reg.
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def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
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@ -146,14 +146,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::AND8rr, X86::AND8mr, 0 },
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{ X86::DEC16r, X86::DEC16m, 0 },
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{ X86::DEC32r, X86::DEC32m, 0 },
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{ X86::DEC64_16r, X86::DEC64_16m, 0 },
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{ X86::DEC64_32r, X86::DEC64_32m, 0 },
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{ X86::DEC64r, X86::DEC64m, 0 },
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{ X86::DEC8r, X86::DEC8m, 0 },
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{ X86::INC16r, X86::INC16m, 0 },
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{ X86::INC32r, X86::INC32m, 0 },
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{ X86::INC64_16r, X86::INC64_16m, 0 },
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{ X86::INC64_32r, X86::INC64_32m, 0 },
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{ X86::INC64r, X86::INC64m, 0 },
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{ X86::INC8r, X86::INC8m, 0 },
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{ X86::NEG16r, X86::NEG16m, 0 },
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@ -2175,11 +2171,9 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
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break;
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}
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case X86::INC16r:
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case X86::INC64_16r:
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addRegOffset(MIB, leaInReg, true, 1);
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break;
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case X86::DEC16r:
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case X86::DEC64_16r:
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addRegOffset(MIB, leaInReg, true, -1);
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break;
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case X86::ADD16ri:
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@ -2332,8 +2326,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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switch (MIOpc) {
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default: return nullptr;
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case X86::INC64r:
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case X86::INC32r:
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case X86::INC64_32r: {
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case X86::INC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
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unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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@ -2354,7 +2347,6 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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break;
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}
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case X86::INC16r:
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case X86::INC64_16r:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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@ -2363,8 +2355,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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.addOperand(Dest).addOperand(Src), 1);
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break;
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case X86::DEC64r:
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case X86::DEC32r:
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case X86::DEC64_32r: {
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case X86::DEC32r: {
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assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
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unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
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: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
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@ -2387,7 +2378,6 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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break;
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}
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case X86::DEC16r:
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case X86::DEC64_16r:
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if (DisableLEA16)
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return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
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: nullptr;
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@ -3718,14 +3708,12 @@ inline static bool isDefConvertible(MachineInstr *MI) {
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case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
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case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
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case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
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case X86::DEC64_32r: case X86::DEC64_16r:
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case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
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case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
|
||||
case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
|
||||
case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
|
||||
case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
|
||||
case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
|
||||
case X86::INC64_32r: case X86::INC64_16r:
|
||||
case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
|
||||
case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
|
||||
case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
|
||||
@ -5476,14 +5464,10 @@ bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
|
||||
return FuseKind == FuseCmp || FuseKind == FuseInc;
|
||||
case X86::INC16r:
|
||||
case X86::INC32r:
|
||||
case X86::INC64_16r:
|
||||
case X86::INC64_32r:
|
||||
case X86::INC64r:
|
||||
case X86::INC8r:
|
||||
case X86::DEC16r:
|
||||
case X86::DEC32r:
|
||||
case X86::DEC64_16r:
|
||||
case X86::DEC64_32r:
|
||||
case X86::DEC64r:
|
||||
case X86::DEC8r:
|
||||
return FuseKind == FuseInc;
|
||||
|
||||
@ -545,6 +545,24 @@ ReSimplify:
|
||||
break;
|
||||
}
|
||||
|
||||
case X86::DEC16r:
|
||||
case X86::DEC32r:
|
||||
case X86::INC16r:
|
||||
case X86::INC32r:
|
||||
// If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
|
||||
if (!AsmPrinter.getSubtarget().is64Bit()) {
|
||||
unsigned Opcode;
|
||||
switch (OutMI.getOpcode()) {
|
||||
default: llvm_unreachable("Invalid opcode");
|
||||
case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
|
||||
case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
|
||||
case X86::INC16r: Opcode = X86::INC16r_alt; break;
|
||||
case X86::INC32r: Opcode = X86::INC32r_alt; break;
|
||||
}
|
||||
OutMI.setOpcode(Opcode);
|
||||
}
|
||||
break;
|
||||
|
||||
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
|
||||
// this with an ugly goto in case the resultant OR uses EAX and needs the
|
||||
// short form.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user