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[GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 types
Summary: Legalize only if the type is marked as Legal or Custom. If not, return Unsupported as LegalizerHelper is not able to handle non-power-of-2 types right now. Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, kristof.beyls, javed.absar, ab Reviewed By: kristof.beyls, ab Subscribers: dberris, rovka, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31711 llvm-svn: 299929
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@ -73,11 +73,6 @@ LegalizerInfo::getAction(const InstrAspect &Aspect) const {
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// These *have* to be implemented for now, they're the fundamental basis of
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// how everything else is transformed.
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// Nothing is going to go well with types that aren't a power of 2 yet, so
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// don't even try because we might make things worse.
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if (!isPowerOf2_64(Aspect.Type.getSizeInBits()))
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return std::make_pair(Unsupported, LLT());
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// FIXME: the long-term plan calls for expansion in terms of load/store (if
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// they're not legal).
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if (Aspect.Opcode == TargetOpcode::G_SEQUENCE ||
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@ -86,12 +81,20 @@ LegalizerInfo::getAction(const InstrAspect &Aspect) const {
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Aspect.Opcode == TargetOpcode::G_UNMERGE_VALUES)
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return std::make_pair(Legal, Aspect.Type);
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LLT Ty = Aspect.Type;
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LegalizeAction Action = findInActions(Aspect);
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// LegalizerHelper is not able to handle non-power-of-2 types right now, so do
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// not try to legalize them unless they are marked as Legal or Custom.
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// FIXME: This is a temporary hack until the general non-power-of-2
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// legalization works.
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if (!isPowerOf2_64(Ty.getSizeInBits()) &&
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!(Action == Legal || Action == Custom))
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return std::make_pair(Unsupported, LLT());
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if (Action != NotFound)
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return findLegalAction(Aspect, Action);
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unsigned Opcode = Aspect.Opcode;
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LLT Ty = Aspect.Type;
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if (!Ty.isVector()) {
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auto DefaultAction = DefaultActions.find(Aspect.Opcode);
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if (DefaultAction != DefaultActions.end() && DefaultAction->second == Legal)
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@ -71,6 +71,14 @@ define void @odd_type(i42* %addr) {
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ret void
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s32>) = G_LOAD %vreg0; mem:LD28[%addr](align=32) (in function: odd_vector)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
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; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
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define void @odd_vector(<7 x i32>* %addr) {
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%vec = load <7 x i32>, <7 x i32>* %addr
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ret void
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}
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; RegBankSelect crashed when given invalid mappings, and AArch64's
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; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
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@ -0,0 +1,29 @@
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# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_legalize_merge_v3s32() {
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ret void
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}
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...
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---
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name: test_legalize_merge_v3s32
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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body: |
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bb.0:
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liveins: %w0, %w1, %w2
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; CHECK-LABEL: name: test_legalize_merge_v3s32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
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; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1
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; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2
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; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32)
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%0(s32) = COPY %w0
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%1(s32) = COPY %w1
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%2(s32) = COPY %w2
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%3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32)
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...
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