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Revert "[AMDGPU] Define special SGPR subregs"
This reverts commit 1baaa080e0481fa2a7cfafc7303c264d0a305c58.
This commit is contained in:
Stanislav Mekhanoshin
parent
277938f1ad
commit
ab8f19a3de
@ -765,7 +765,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
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}
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if (AMDGPU::SReg_32RegClass.contains(Reg) ||
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AMDGPU::SReg_LO16RegClass.contains(Reg) ||
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AMDGPU::SGPR_LO16RegClass.contains(Reg) ||
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AMDGPU::SGPR_HI16RegClass.contains(Reg)) {
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assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
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"trap handler registers should not be used");
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@ -7,7 +7,7 @@
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//===----------------------------------------------------------------------===//
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def SGPRRegBank : RegisterBank<"SGPR",
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[SReg_LO16, SReg_32, SReg_64, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
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[SGPR_LO16, SReg_32, SReg_64, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
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>;
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def VGPRRegBank : RegisterBank<"VGPR",
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@ -678,20 +678,21 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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return;
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}
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if (RI.getRegSizeInBits(*RC) == 16) {
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if (RC == &AMDGPU::VGPR_LO16RegClass || RC == &AMDGPU::VGPR_HI16RegClass ||
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RC == &AMDGPU::SGPR_LO16RegClass) {
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assert(AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
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AMDGPU::VGPR_HI16RegClass.contains(SrcReg) ||
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AMDGPU::SReg_LO16RegClass.contains(SrcReg));
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AMDGPU::SGPR_LO16RegClass.contains(SrcReg));
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bool IsSGPRDst = AMDGPU::SReg_LO16RegClass.contains(DestReg);
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bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
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bool DstLow = AMDGPU::VGPR_LO16RegClass.contains(DestReg) ||
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AMDGPU::SReg_LO16RegClass.contains(DestReg);
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bool IsSGPRDst = AMDGPU::SGPR_LO16RegClass.contains(DestReg);
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bool IsSGPRSrc = AMDGPU::SGPR_LO16RegClass.contains(SrcReg);
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bool DstLow = (RC == &AMDGPU::VGPR_LO16RegClass ||
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RC == &AMDGPU::SGPR_LO16RegClass);
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bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
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AMDGPU::SReg_LO16RegClass.contains(SrcReg);
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const TargetRegisterClass *DstRC = IsSGPRDst ? &AMDGPU::SReg_32RegClass
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AMDGPU::SGPR_LO16RegClass.contains(SrcReg);
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const TargetRegisterClass *DstRC = IsSGPRDst ? &AMDGPU::SGPR_32RegClass
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: &AMDGPU::VGPR_32RegClass;
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const TargetRegisterClass *SrcRC = IsSGPRSrc ? &AMDGPU::SReg_32RegClass
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const TargetRegisterClass *SrcRC = IsSGPRSrc ? &AMDGPU::SGPR_32RegClass
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: &AMDGPU::VGPR_32RegClass;
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MCRegister NewDestReg =
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RI.getMatchingSuperReg(DestReg, DstLow ? AMDGPU::lo16 : AMDGPU::hi16,
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@ -263,14 +263,6 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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reserveRegisterTuples(Reserved, Reg);
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}
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for (auto Reg : AMDGPU::SReg_32RegClass) {
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Reserved.set(getSubReg(Reg, AMDGPU::hi16));
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Register Low = getSubReg(Reg, AMDGPU::lo16);
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// This is to prevent BB vcc liveness errors.
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if (!AMDGPU::SGPR_LO16RegClass.contains(Low))
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Reserved.set(Low);
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}
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// Reserve all the rest AGPRs if there are no instructions to use it.
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if (!ST.hasMAIInsts()) {
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for (unsigned i = 0; i < MaxNumVGPRs; ++i) {
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@ -1373,7 +1365,7 @@ SIRegisterInfo::getPhysRegClass(MCRegister Reg) const {
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static const TargetRegisterClass *const BaseClasses[] = {
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&AMDGPU::VGPR_LO16RegClass,
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&AMDGPU::VGPR_HI16RegClass,
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&AMDGPU::SReg_LO16RegClass,
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&AMDGPU::SGPR_LO16RegClass,
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&AMDGPU::VGPR_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::AGPR_32RegClass,
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@ -123,41 +123,25 @@ class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
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class SIReg <string n, bits<16> regIdx = 0> :
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Register<n> {
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let Namespace = "AMDGPU";
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// This is the not yet the complete register encoding. An additional
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// bit is set for VGPRs.
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let HWEncoding = regIdx;
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}
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class SIRegWithSubRegs <string n, list<Register> subregs, bits<16> regIdx> :
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class SIRegWithSubRegs <string n, list<Register> subregs, bits<16> regIdx = 0> :
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RegisterWithSubRegs<n, subregs> {
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}
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let Namespace = "AMDGPU";
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multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
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bit HWEncodingHigh = 0> {
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// There is no special encoding for 16 bit subregs, these are not real
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// registers but rather operands for instructions preserving other 16 bits
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// of the result or reading just 16 bits of a 32 bit VGPR.
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// It is encoded as a corresponding 32 bit register.
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// Non-VGPR register classes use it as we need to have matching subregisters
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// to move instructions and data between ALUs.
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def _LO16 : SIReg<n#".l", regIdx> {
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let HWEncoding{8} = HWEncodingHigh;
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}
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def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx> {
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let isArtificial = ArtificialHigh;
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let HWEncoding{8} = HWEncodingHigh;
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}
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def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
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!cast<Register>(NAME#"_HI16")]> {
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let Namespace = "AMDGPU";
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let SubRegIndices = [lo16, hi16];
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let CoveredBySubRegs = 1;
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let HWEncoding = regIdx;
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let HWEncoding{8} = HWEncodingHigh;
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}
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// This is the not yet the complete register encoding. An additional
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// bit is set for VGPRs.
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let HWEncoding = regIdx;
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let CoveredBySubRegs = 1;
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}
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// Special Registers
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defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;
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defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;
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def VCC_LO : SIReg<"vcc_lo", 106>;
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def VCC_HI : SIReg<"vcc_hi", 107>;
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// Pseudo-registers: Used as placeholders during isel and immediately
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// replaced, never seeing the verifier.
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@ -180,8 +164,8 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
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let HWEncoding = 106;
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}
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defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
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defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>;
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def EXEC_LO : SIReg<"exec_lo", 126>, DwarfRegNum<[1, 1]>;
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def EXEC_HI : SIReg<"exec_hi", 127>;
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def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
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let Namespace = "AMDGPU";
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@ -191,22 +175,22 @@ def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]>
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// 32-bit real registers, for MC only.
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// May be used with both 32-bit and 64-bit operands.
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defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>;
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defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>;
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defm SRC_SCC : SIRegLoHi16<"src_scc", 253>;
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def SRC_VCCZ : SIReg<"src_vccz", 251>;
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def SRC_EXECZ : SIReg<"src_execz", 252>;
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def SRC_SCC : SIReg<"src_scc", 253>;
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// 1-bit pseudo register, for codegen only.
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// Should never be emitted.
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def SCC : SIReg<"scc">;
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defm M0 : SIRegLoHi16 <"m0", 124>;
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defm SGPR_NULL : SIRegLoHi16 <"null", 125>;
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def M0 : SIReg <"m0", 124>;
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def SGPR_NULL : SIReg<"null", 125>;
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defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>;
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defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>;
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defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>;
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defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>;
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defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
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def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>;
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def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>;
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def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>;
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def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>;
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def SRC_POPS_EXITING_WAVE_ID : SIReg<"src_pops_exiting_wave_id", 239>;
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def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
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// There is no physical register corresponding to this. This is an
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@ -215,8 +199,8 @@ def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
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let isArtificial = 1;
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}
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defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>;
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defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>;
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def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>;
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def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>;
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def XNACK_MASK :
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RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> {
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@ -226,8 +210,8 @@ def XNACK_MASK :
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}
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// Trap handler registers
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defm TBA_LO : SIRegLoHi16<"tba_lo", 108>;
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defm TBA_HI : SIRegLoHi16<"tba_hi", 109>;
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def TBA_LO : SIReg<"tba_lo", 108>;
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def TBA_HI : SIReg<"tba_hi", 109>;
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def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {
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let Namespace = "AMDGPU";
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@ -235,8 +219,8 @@ def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {
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let HWEncoding = 108;
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}
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defm TMA_LO : SIRegLoHi16<"tma_lo", 110>;
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defm TMA_HI : SIRegLoHi16<"tma_hi", 111>;
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def TMA_LO : SIReg<"tma_lo", 110>;
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def TMA_HI : SIReg<"tma_hi", 111>;
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def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
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let Namespace = "AMDGPU";
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@ -245,15 +229,15 @@ def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
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}
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foreach Index = 0-15 in {
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defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>;
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defm TTMP#Index#_gfx9_gfx10 : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>;
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defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>;
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def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>;
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def TTMP#Index#_gfx9_gfx10 : SIReg<"ttmp"#Index, !add(108, Index)>;
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def TTMP#Index : SIReg<"ttmp"#Index, 0>;
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}
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multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
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defm _ci : SIRegLoHi16<n, ci_e>;
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defm _vi : SIRegLoHi16<n, vi_e>;
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defm "" : SIRegLoHi16<n, 0>;
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def _ci : SIReg<n, ci_e>;
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def _vi : SIReg<n, vi_e>;
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def "" : SIReg<n, 0>;
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}
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class FlatReg <Register lo, Register hi, bits<16> encoding> :
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@ -272,17 +256,50 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
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// SGPR registers
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foreach Index = 0-105 in {
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defm SGPR#Index :
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SIRegLoHi16 <"s"#Index, Index>,
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DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
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!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
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def SGPR#Index#_LO16 : SIReg <"s"#Index#".l", Index>,
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DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
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!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
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// This is a placeholder to fill high lane in mask.
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def SGPR#Index#_HI16 : SIReg <"", Index> {
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let isArtificial = 1;
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}
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def SGPR#Index :
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SIRegWithSubRegs <"s"#Index, [!cast<Register>("SGPR"#Index#"_LO16"),
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!cast<Register>("SGPR"#Index#"_HI16")],
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Index>,
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DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
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!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]> {
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let SubRegIndices = [lo16, hi16];
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}
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}
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// VGPR registers
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foreach Index = 0-255 in {
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defm VGPR#Index :
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SIRegLoHi16 <"v"#Index, Index, 0, 1>,
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DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>;
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// There is no special encoding for low 16 bit subreg, this not a real
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// register but rather an operand for instructions preserving high 16 bits
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// of the result or reading just low 16 bits of a 32 bit VGPR.
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// It is encoded as a corresponding 32 bit register.
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def VGPR#Index#_LO16 : SIReg <"v"#Index#".l", Index>,
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DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]> {
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let HWEncoding{8} = 1;
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}
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// There is no special encoding for low 16 bit subreg, this not a real
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// register but rather an operand for instructions preserving low 16 bits
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// of the result or reading just high 16 bits of a 32 bit VGPR.
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// It is encoded as a corresponding 32 bit register.
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def VGPR#Index#_HI16 : SIReg <"v"#Index#".h", Index>,
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DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]> {
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let HWEncoding{8} = 1;
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}
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def VGPR#Index : SIRegWithSubRegs <"v"#Index,
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[!cast<Register>("VGPR"#Index#"_LO16"), !cast<Register>("VGPR"#Index#"_HI16")],
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Index>,
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DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]> {
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let HWEncoding{8} = 1;
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let SubRegIndices = [lo16, hi16];
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}
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}
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// AccVGPR registers
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@ -308,17 +325,11 @@ def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
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let isAllocatable = 0;
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}
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def M0_CLASS_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16, (add M0_LO16)> {
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let CopyCost = 1;
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let Size = 16;
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let isAllocatable = 0;
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}
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// TODO: Do we need to set DwarfRegAlias on register tuples?
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def SGPR_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16,
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(add (sequence "SGPR%u_LO16", 0, 105))> {
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let AllocationPriority = 9;
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let AllocationPriority = 1;
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let Size = 16;
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let GeneratePressureSet = 0;
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}
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@ -369,12 +380,6 @@ def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
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let isAllocatable = 0;
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}
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def TTMP_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16,
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(add (sequence "TTMP%u_LO16", 0, 15))> {
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let Size = 16;
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let isAllocatable = 0;
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}
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// Trap handler TMP 64-bit registers
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def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">;
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@ -583,43 +588,15 @@ def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f1
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let AllocationPriority = 10;
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}
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def SReg_LO16_XM0_XEXEC : RegisterClass<"AMDGPU", [i16, f16], 16,
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(add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16,
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XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, TTMP_LO16, TMA_LO_LO16,
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TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO16,
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SRC_SHARED_LIMIT_LO16, SRC_PRIVATE_BASE_LO16, SRC_PRIVATE_LIMIT_LO16,
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SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16)> {
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let Size = 16;
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let AllocationPriority = 10;
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}
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def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
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(add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> {
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let AllocationPriority = 10;
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}
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def SReg_LO16_XEXEC_HI : RegisterClass<"AMDGPU", [i16, f16], 16,
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(add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, M0_CLASS_LO16)> {
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let Size = 16;
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let AllocationPriority = 10;
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}
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def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
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(add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
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||||
let AllocationPriority = 10;
|
||||
}
|
||||
|
||||
def SReg_LO16_XM0 : RegisterClass<"AMDGPU", [i16, f16], 16,
|
||||
(add SReg_LO16_XM0_XEXEC, EXEC_LO_LO16, EXEC_HI_LO16)> {
|
||||
let Size = 16;
|
||||
let AllocationPriority = 10;
|
||||
}
|
||||
|
||||
def SReg_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16,
|
||||
(add SGPR_LO16, SReg_LO16_XM0, M0_CLASS_LO16, EXEC_LO_LO16, EXEC_HI_LO16, SReg_LO16_XEXEC_HI)> {
|
||||
let Size = 16;
|
||||
let AllocationPriority = 10;
|
||||
}
|
||||
} // End GeneratePressureSet = 0
|
||||
|
||||
// Register class for all scalar registers (SGPRs + Special Registers)
|
||||
|
||||
@ -24,13 +24,13 @@ define void @nothing() #0 {
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-DAG: special_regs Clobbered Registers: $scc $m0 $m0_hi16 $m0_lo16 {{$}}
|
||||
; CHECK-DAG: special_regs Clobbered Registers: $scc $m0 {{$}}
|
||||
define void @special_regs() #0 {
|
||||
call void asm sideeffect "", "~{m0},~{scc}"() #0
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-DAG: vcc Clobbered Registers: $vcc $vcc_hi $vcc_lo $vcc_hi_hi16 $vcc_hi_lo16 $vcc_lo_hi16 $vcc_lo_lo16 {{$}}
|
||||
; CHECK-DAG: vcc Clobbered Registers: $vcc $vcc_hi $vcc_lo {{$}}
|
||||
define void @vcc() #0 {
|
||||
call void asm sideeffect "", "~{vcc}"() #0
|
||||
ret void
|
||||
|
||||
@ -33,7 +33,7 @@ body: |
|
||||
; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
|
||||
; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def dead [[COPY1]], 851978 /* regdef:SReg_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:SGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
|
||||
; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
|
||||
; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
|
||||
; CHECK: dead %10:vgpr_32 = V_ADD_I32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
|
||||
|
||||
@ -36,18 +36,18 @@ body: |
|
||||
; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def dead %11
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def dead %11
|
||||
; CHECK: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
|
||||
; CHECK: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; CHECK: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; CHECK: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
|
||||
; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %15, 851978 /* regdef:SReg_LO16 */, def %16
|
||||
; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def %15, 851978 /* regdef:SGPR_LO16 */, def %16
|
||||
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
|
||||
; CHECK: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
|
||||
; CHECK: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
|
||||
; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %21, 851978 /* regdef:SReg_LO16 */, def %22
|
||||
; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def %21, 851978 /* regdef:SGPR_LO16 */, def %22
|
||||
; CHECK: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:SReg_LO16 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:SReg_LO16 */, %15, 851977 /* reguse:SReg_LO16 */, %16, 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_2]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:SGPR_LO16 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:SGPR_LO16 */, %15, 851977 /* reguse:SGPR_LO16 */, %16, 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B32_gfx9_2]]
|
||||
; CHECK: %5.sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
|
||||
; CHECK: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
|
||||
; CHECK: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
|
||||
|
||||
@ -25,9 +25,9 @@ body: |
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def undef %0.sub0, 851978 /* regdef:SReg_LO16 */, def undef %0.sub1
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B32_gfx9_]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def undef %0.sub0, 851978 /* regdef:SGPR_LO16 */, def undef %0.sub1
|
||||
; CHECK: S_NOP 0, implicit %0.sub1
|
||||
; CHECK: $sgpr10 = S_MOV_B32 -1
|
||||
; CHECK: S_BRANCH %bb.1
|
||||
@ -63,9 +63,9 @@ body: |
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def undef %0.sub1, 851978 /* regdef:SReg_LO16 */, def undef %0.sub0
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:SGPR_LO16 */, [[DS_READ_B32_gfx9_]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SGPR_LO16 */, def undef %0.sub1, 851978 /* regdef:SGPR_LO16 */, def undef %0.sub0
|
||||
; CHECK: S_NOP 0, implicit %0.sub1
|
||||
; CHECK: $sgpr10 = S_MOV_B32 -1
|
||||
; CHECK: S_BRANCH %bb.1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user