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[MCA] Introduce class LSUnitBase and let LSUnit derive from it.
Class LSUnitBase provides a abstract interface for all the concrete LS units in llvm-mca. Methods exposed by the public abstract LSUnitBase interface are: - Status isAvailable(const InstRef&); - void dispatch(const InstRef &); - const InstRef &isReady(const InstRef &); LSUnitBase standardises the API, but not the data structures internally used by LS units. This allows for more flexibility. Previously, only method `isReady()` was declared virtual by class LSUnit. Also, derived classes had to inherit all the internal data members of LSUnit. No functional change intended. llvm-svn: 361496
This commit is contained in:
Andrea Di Biagio
parent
1504131bb7
commit
aba464655a
@ -18,13 +18,83 @@
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
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#include "llvm/MCA/Instruction.h"
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namespace llvm {
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namespace mca {
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class InstRef;
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class Scheduler;
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/// Abstract base interface for LS (load/store) units in llvm-mca.
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class LSUnitBase : public HardwareUnit {
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/// Load queue size.
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///
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/// A value of zero for this field means that the load queue is unbounded.
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/// Processor models can declare the size of a load queue via tablegen (see
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/// the definition of tablegen class LoadQueue in
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/// llvm/Target/TargetSchedule.td).
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unsigned LQSize;
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/// Load queue size.
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///
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/// A value of zero for this field means that the store queue is unbounded.
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/// Processor models can declare the size of a store queue via tablegen (see
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/// the definition of tablegen class StoreQueue in
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/// llvm/Target/TargetSchedule.td).
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unsigned SQSize;
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/// True if loads don't alias with stores.
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///
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/// By default, the LS unit assumes that loads and stores don't alias with
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/// eachother. If this field is set to false, then loads are always assumed to
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/// alias with stores.
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const bool NoAlias;
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public:
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LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize,
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unsigned StoreQueueSize, bool AssumeNoAlias);
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virtual ~LSUnitBase();
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/// Returns the total number of entries in the load queue.
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unsigned getLoadQueueSize() const { return LQSize; }
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/// Returns the total number of entries in the store queue.
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unsigned getStoreQueueSize() const { return SQSize; }
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bool assumeNoAlias() const { return NoAlias; }
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enum Status {
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LSU_AVAILABLE = 0,
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LSU_LQUEUE_FULL, // Load Queue unavailable
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LSU_SQUEUE_FULL // Store Queue unavailable
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};
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/// This method checks the availability of the load/store buffers.
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///
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/// Returns LSU_AVAILABLE if there are enough load/store queue entries to
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/// accomodate instruction IR. By default, LSU_AVAILABLE is returned if IR is
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/// not a memory operation.
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virtual Status isAvailable(const InstRef &IR) const = 0;
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/// Allocates LS resources for instruction IR.
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///
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/// This method assumes that a previous call to `isAvailable(IR)` succeeded
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/// with a LSUnitBase::Status value of LSU_AVAILABLE.
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virtual void dispatch(const InstRef &IR) = 0;
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/// Check if a peviously dispatched instruction IR is now ready for execution.
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///
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/// Instruction IR is assumed to be a memory operation. If IR is still waiting
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/// on another memory instruction M, then M is returned to the caller. If IR
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/// depends on more than one memory operations, then this method returns one
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/// of them.
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///
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/// Derived classes can implement memory consistency rules for simulated
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/// processor within this member function.
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virtual const InstRef &isReady(const InstRef &IR) const = 0;
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};
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/// A Load/Store Unit implementing a load and store queues.
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///
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/// This class implements a load queue and a store queue to emulate the
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@ -88,18 +158,7 @@ class Scheduler;
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/// A load/store barrier is "executed" when it becomes the oldest entry in
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/// the load/store queue(s). That also means, all the older loads/stores have
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/// already been executed.
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class LSUnit : public HardwareUnit {
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// Load queue size.
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// LQ_Size == 0 means that there are infinite slots in the load queue.
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unsigned LQ_Size;
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// Store queue size.
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// SQ_Size == 0 means that there are infinite slots in the store queue.
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unsigned SQ_Size;
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// If true, loads will never alias with stores. This is the default.
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bool NoAlias;
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class LSUnit : public LSUnitBase {
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// When a `MayLoad` instruction is dispatched to the schedulers for execution,
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// the LSUnit reserves an entry in the `LoadQueue` for it.
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//
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@ -138,68 +197,75 @@ class LSUnit : public HardwareUnit {
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// alternative approaches that let instructions specify the number of
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// load/store queue entries which they consume at dispatch stage (See
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// PR39830).
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SmallSet<unsigned, 16> LoadQueue;
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SmallSet<unsigned, 16> StoreQueue;
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SmallSet<InstRef, 16> LoadQueue;
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SmallSet<InstRef, 16> StoreQueue;
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void assignLQSlot(unsigned Index);
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void assignSQSlot(unsigned Index);
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void assignLQSlot(const InstRef &IR);
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void assignSQSlot(const InstRef &IR);
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// An instruction that both 'mayStore' and 'HasUnmodeledSideEffects' is
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// conservatively treated as a store barrier. It forces older store to be
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// executed before newer stores are issued.
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SmallSet<unsigned, 8> StoreBarriers;
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SmallSet<InstRef, 8> StoreBarriers;
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// An instruction that both 'MayLoad' and 'HasUnmodeledSideEffects' is
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// conservatively treated as a load barrier. It forces older loads to execute
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// before newer loads are issued.
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SmallSet<unsigned, 8> LoadBarriers;
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SmallSet<InstRef, 8> LoadBarriers;
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bool isSQEmpty() const { return StoreQueue.empty(); }
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bool isLQEmpty() const { return LoadQueue.empty(); }
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bool isSQFull() const { return SQ_Size != 0 && StoreQueue.size() == SQ_Size; }
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bool isLQFull() const { return LQ_Size != 0 && LoadQueue.size() == LQ_Size; }
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bool isSQFull() const {
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return getStoreQueueSize() != 0 && StoreQueue.size() == getStoreQueueSize();
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}
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bool isLQFull() const {
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return getLoadQueueSize() != 0 && LoadQueue.size() == getLoadQueueSize();
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}
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public:
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LSUnit(const MCSchedModel &SM, unsigned LQ = 0, unsigned SQ = 0,
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bool AssumeNoAlias = false);
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LSUnit(const MCSchedModel &SM)
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: LSUnit(SM, /* LQSize */ 0, /* SQSize */ 0, /* NoAlias */ false) {}
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LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ)
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: LSUnit(SM, LQ, SQ, /* NoAlias */ false) {}
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LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ, bool AssumeNoAlias)
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: LSUnitBase(SM, LQ, SQ, AssumeNoAlias) {}
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#ifndef NDEBUG
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void dump() const;
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#endif
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enum Status { LSU_AVAILABLE = 0, LSU_LQUEUE_FULL, LSU_SQUEUE_FULL };
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/// Returns LSU_AVAILABLE if there are enough load/store queue entries to
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/// accomodate instruction IR.
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Status isAvailable(const InstRef &IR) const override;
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// Returns LSU_AVAILABLE if there are enough load/store queue entries to serve
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// IR. It also returns LSU_AVAILABLE if IR is not a memory operation.
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Status isAvailable(const InstRef &IR) const;
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/// Allocates LS resources for instruction IR.
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///
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/// This method assumes that a previous call to `isAvailable(IR)` succeeded
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/// returning LSU_AVAILABLE.
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void dispatch(const InstRef &IR) override;
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// Allocates load/store queue resources for IR.
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//
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// This method assumes that a previous call to `isAvailable(IR)` returned
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// LSU_AVAILABLE, and that IR is a memory operation.
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void dispatch(const InstRef &IR);
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/// Check if a peviously dispatched instruction IR is now ready for execution.
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///
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/// Rules are:
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/// By default, rules are:
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/// 1. A store may not pass a previous store.
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/// 2. A load may not pass a previous store unless flag 'NoAlias' is set.
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/// 3. A load may pass a previous load.
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/// 4. A store may not pass a previous load (regardless of flag 'NoAlias').
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/// 5. A load has to wait until an older load barrier is fully executed.
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/// 6. A store has to wait until an older store barrier is fully executed.
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const InstRef &isReady(const InstRef &IR) const override;
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// By default, rules are:
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// 1. A store may not pass a previous store.
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// 2. A load may not pass a previous store unless flag 'NoAlias' is set.
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// 3. A load may pass a previous load.
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// 4. A store may not pass a previous load (regardless of flag 'NoAlias').
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// 5. A load has to wait until an older load barrier is fully executed.
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// 6. A store has to wait until an older store barrier is fully executed.
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//
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// Returns an instruction identifier. If IR is ready, then this method returns
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// `IR.getSourceIndex()`. Otherwise it returns the instruction ID of the
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// dependent (i.e. conflicting) memory instruction.
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virtual unsigned isReady(const InstRef &IR) const;
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// Load and store instructions are tracked by their corresponding queues from
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// dispatch until the "instruction executed" event.
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// Only when a load instruction reaches the 'Executed' stage, its value
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// becomes available to the users. At that point, the load no longer needs to
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// be tracked by the load queue.
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// FIXME: For simplicity, we optimistically assume a similar behavior for
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// store instructions. In practice, store operations don't tend to leave the
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// store queue until they reach the 'Retired' stage (See PR39830).
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/// Instruction executed event handler.
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///
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/// Load and store instructions are tracked by their corresponding queues from
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/// dispatch until "instruction executed" event.
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/// When a load instruction Ld reaches the 'Executed' stage, its value
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/// is propagated to all the dependent users, and the LS unit stops tracking
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/// Ld.
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/// FIXME: For simplicity, we optimistically assume a similar behavior for
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/// store instructions. In practice, store operations don't tend to leave the
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/// store queue until they reach the 'Retired' stage (See PR39830).
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void onInstructionExecuted(const InstRef &IR);
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};
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@ -21,48 +21,48 @@
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namespace llvm {
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namespace mca {
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LSUnit::LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ,
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bool AssumeNoAlias)
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: LQ_Size(LQ), SQ_Size(SQ), NoAlias(AssumeNoAlias) {
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LSUnitBase::LSUnitBase(const MCSchedModel &SM, unsigned LQ, unsigned SQ,
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bool AssumeNoAlias)
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: LQSize(LQ), SQSize(SQ), NoAlias(AssumeNoAlias) {
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if (SM.hasExtraProcessorInfo()) {
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const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
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if (!LQ_Size && EPI.LoadQueueID) {
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if (!LQSize && EPI.LoadQueueID) {
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const MCProcResourceDesc &LdQDesc = *SM.getProcResource(EPI.LoadQueueID);
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LQ_Size = LdQDesc.BufferSize;
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LQSize = LdQDesc.BufferSize;
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}
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if (!SQ_Size && EPI.StoreQueueID) {
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if (!SQSize && EPI.StoreQueueID) {
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const MCProcResourceDesc &StQDesc = *SM.getProcResource(EPI.StoreQueueID);
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SQ_Size = StQDesc.BufferSize;
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SQSize = StQDesc.BufferSize;
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}
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}
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}
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LSUnitBase::~LSUnitBase() {}
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#ifndef NDEBUG
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void LSUnit::dump() const {
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dbgs() << "[LSUnit] LQ_Size = " << LQ_Size << '\n';
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dbgs() << "[LSUnit] SQ_Size = " << SQ_Size << '\n';
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dbgs() << "[LSUnit] LQ_Size = " << getLoadQueueSize() << '\n';
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dbgs() << "[LSUnit] SQ_Size = " << getStoreQueueSize() << '\n';
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dbgs() << "[LSUnit] NextLQSlotIdx = " << LoadQueue.size() << '\n';
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dbgs() << "[LSUnit] NextSQSlotIdx = " << StoreQueue.size() << '\n';
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}
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#endif
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void LSUnit::assignLQSlot(unsigned Index) {
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assert(!isLQFull());
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assert(LoadQueue.count(Index) == 0);
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void LSUnit::assignLQSlot(const InstRef &IR) {
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assert(!isLQFull() && "Load Queue is full!");
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LLVM_DEBUG(dbgs() << "[LSUnit] - AssignLQSlot <Idx=" << Index
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LLVM_DEBUG(dbgs() << "[LSUnit] - AssignLQSlot <Idx=" << IR.getSourceIndex()
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<< ",slot=" << LoadQueue.size() << ">\n");
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LoadQueue.insert(Index);
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LoadQueue.insert(IR);
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}
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void LSUnit::assignSQSlot(unsigned Index) {
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assert(!isSQFull());
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assert(StoreQueue.count(Index) == 0);
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void LSUnit::assignSQSlot(const InstRef &IR) {
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assert(!isSQFull() && "Store Queue is full!");
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LLVM_DEBUG(dbgs() << "[LSUnit] - AssignSQSlot <Idx=" << Index
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LLVM_DEBUG(dbgs() << "[LSUnit] - AssignSQSlot <Idx=" << IR.getSourceIndex()
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<< ",slot=" << StoreQueue.size() << ">\n");
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StoreQueue.insert(Index);
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StoreQueue.insert(IR);
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}
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void LSUnit::dispatch(const InstRef &IR) {
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@ -70,17 +70,16 @@ void LSUnit::dispatch(const InstRef &IR) {
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unsigned IsMemBarrier = Desc.HasSideEffects;
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assert((Desc.MayLoad || Desc.MayStore) && "Not a memory operation!");
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const unsigned Index = IR.getSourceIndex();
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if (Desc.MayLoad) {
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if (IsMemBarrier)
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LoadBarriers.insert(Index);
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assignLQSlot(Index);
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LoadBarriers.insert(IR);
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assignLQSlot(IR);
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}
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if (Desc.MayStore) {
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if (IsMemBarrier)
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StoreBarriers.insert(Index);
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assignSQSlot(Index);
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StoreBarriers.insert(IR);
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assignSQSlot(IR);
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}
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}
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@ -93,65 +92,67 @@ LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const {
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return LSUnit::LSU_AVAILABLE;
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}
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unsigned LSUnit::isReady(const InstRef &IR) const {
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const InstRef &LSUnit::isReady(const InstRef &IR) const {
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const InstrDesc &Desc = IR.getInstruction()->getDesc();
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const unsigned Index = IR.getSourceIndex();
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bool IsALoad = Desc.MayLoad;
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bool IsAStore = Desc.MayStore;
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assert((IsALoad || IsAStore) && "Not a memory operation!");
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assert((!IsALoad || LoadQueue.count(Index) == 1) && "Load not in queue!");
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assert((!IsAStore || StoreQueue.count(Index) == 1) && "Store not in queue!");
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if (IsALoad && !LoadBarriers.empty()) {
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unsigned LoadBarrierIndex = *LoadBarriers.begin();
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const InstRef &LoadBarrier = *LoadBarriers.begin();
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// A younger load cannot pass a older load barrier.
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if (Index > LoadBarrierIndex)
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return LoadBarrierIndex;
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if (Index > LoadBarrier.getSourceIndex())
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return LoadBarrier;
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// A load barrier cannot pass a older load.
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if (Index == LoadBarrierIndex && Index != *LoadQueue.begin())
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return *LoadQueue.begin();
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if (Index == LoadBarrier.getSourceIndex()) {
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const InstRef &Load = *LoadQueue.begin();
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if (Index != Load.getSourceIndex())
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return Load;
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}
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}
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if (IsAStore && !StoreBarriers.empty()) {
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unsigned StoreBarrierIndex = *StoreBarriers.begin();
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const InstRef &StoreBarrier = *StoreBarriers.begin();
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// A younger store cannot pass a older store barrier.
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if (Index > StoreBarrierIndex)
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return StoreBarrierIndex;
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if (Index > StoreBarrier.getSourceIndex())
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return StoreBarrier;
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// A store barrier cannot pass a older store.
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if (Index == StoreBarrierIndex && Index != *StoreQueue.begin())
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return *StoreQueue.begin();
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if (Index == StoreBarrier.getSourceIndex()) {
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const InstRef &Store = *StoreQueue.begin();
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if (Index != Store.getSourceIndex())
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return Store;
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}
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}
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// A load may not pass a previous store unless flag 'NoAlias' is set.
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// A load may pass a previous load.
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if (NoAlias && IsALoad)
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return Index;
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if (assumeNoAlias() && IsALoad)
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return IR;
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if (StoreQueue.size()) {
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// A load may not pass a previous store.
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// A store may not pass a previous store.
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if (Index > *StoreQueue.begin())
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return *StoreQueue.begin();
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const InstRef &Store = *StoreQueue.begin();
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if (Index > Store.getSourceIndex())
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return Store;
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}
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// Okay, we are older than the oldest store in the queue.
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// If there are no pending loads, then we can say for sure that this
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// instruction is ready.
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if (isLQEmpty())
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return Index;
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return IR;
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// Check if there are no older loads.
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if (Index <= *LoadQueue.begin())
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return Index;
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const InstRef &Load = *LoadQueue.begin();
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if (Index <= Load.getSourceIndex())
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return IR;
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// There is at least one younger load.
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//
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// A load may pass a previous load.
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if (IsALoad)
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return Index;
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return IR;
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// A store may not pass a previous load.
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return *LoadQueue.begin();
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return Load;
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}
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void LSUnit::onInstructionExecuted(const InstRef &IR) {
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@ -161,29 +162,35 @@ void LSUnit::onInstructionExecuted(const InstRef &IR) {
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bool IsAStore = Desc.MayStore;
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if (IsALoad) {
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if (LoadQueue.erase(Index)) {
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if (LoadQueue.erase(IR)) {
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LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
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<< " has been removed from the load queue.\n");
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}
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if (!LoadBarriers.empty() && Index == *LoadBarriers.begin()) {
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LLVM_DEBUG(
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dbgs() << "[LSUnit]: Instruction idx=" << Index
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<< " has been removed from the set of load barriers.\n");
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LoadBarriers.erase(Index);
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if (!LoadBarriers.empty()) {
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const InstRef &LoadBarrier = *LoadBarriers.begin();
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if (Index == LoadBarrier.getSourceIndex()) {
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LLVM_DEBUG(
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dbgs() << "[LSUnit]: Instruction idx=" << Index
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<< " has been removed from the set of load barriers.\n");
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LoadBarriers.erase(IR);
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}
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}
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}
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if (IsAStore) {
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||||
if (StoreQueue.erase(Index)) {
|
||||
if (StoreQueue.erase(IR)) {
|
||||
LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
|
||||
<< " has been removed from the store queue.\n");
|
||||
}
|
||||
|
||||
if (!StoreBarriers.empty() && Index == *StoreBarriers.begin()) {
|
||||
LLVM_DEBUG(
|
||||
dbgs() << "[LSUnit]: Instruction idx=" << Index
|
||||
<< " has been removed from the set of store barriers.\n");
|
||||
StoreBarriers.erase(Index);
|
||||
if (!StoreBarriers.empty()) {
|
||||
const InstRef &StoreBarrier = *StoreBarriers.begin();
|
||||
if (Index == StoreBarrier.getSourceIndex()) {
|
||||
LLVM_DEBUG(
|
||||
dbgs() << "[LSUnit]: Instruction idx=" << Index
|
||||
<< " has been removed from the set of store barriers.\n");
|
||||
StoreBarriers.erase(IR);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -119,9 +119,9 @@ bool Scheduler::promoteToReadySet(SmallVectorImpl<InstRef> &Ready) {
|
||||
// Check if there are still unsolved memory dependencies.
|
||||
Instruction &IS = *IR.getInstruction();
|
||||
if (IS.isMemOp()) {
|
||||
unsigned CriticalMemDep = LSU.isReady(IR);
|
||||
if (CriticalMemDep != IR.getSourceIndex()) {
|
||||
IS.setCriticalMemDep(CriticalMemDep);
|
||||
const InstRef &CriticalMemDep = LSU.isReady(IR);
|
||||
if (CriticalMemDep != IR) {
|
||||
IS.setCriticalMemDep(CriticalMemDep.getSourceIndex());
|
||||
++I;
|
||||
continue;
|
||||
}
|
||||
@ -158,7 +158,7 @@ bool Scheduler::promoteToPendingSet(SmallVectorImpl<InstRef> &Pending) {
|
||||
break;
|
||||
|
||||
// Check if this instruction is now ready. In case, force
|
||||
// a transition in state using method 'update()'.
|
||||
// a transition in state using method 'updateDispatched()'.
|
||||
Instruction &IS = *IR.getInstruction();
|
||||
if (IS.isDispatched() && !IS.updateDispatched()) {
|
||||
++I;
|
||||
@ -242,12 +242,10 @@ void Scheduler::analyzeDataDependencies(SmallVectorImpl<InstRef> &RegDeps,
|
||||
if (Resources->checkAvailability(IS.getDesc()))
|
||||
continue;
|
||||
|
||||
if (IS.isReady() ||
|
||||
(IS.isMemOp() && LSU.isReady(IR) != IR.getSourceIndex())) {
|
||||
if (IS.isReady() || (IS.isMemOp() && LSU.isReady(IR) != IR))
|
||||
MemDeps.emplace_back(IR);
|
||||
} else {
|
||||
else
|
||||
RegDeps.emplace_back(IR);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -304,8 +302,7 @@ bool Scheduler::dispatch(const InstRef &IR) {
|
||||
|
||||
// Memory operations that are not in a ready state are initially assigned to
|
||||
// the WaitSet.
|
||||
if (!IS.isReady() ||
|
||||
(IS.isMemOp() && LSU.isReady(IR) != IR.getSourceIndex())) {
|
||||
if (!IS.isReady() || (IS.isMemOp() && LSU.isReady(IR) != IR)) {
|
||||
LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
|
||||
WaitSet.push_back(IR);
|
||||
return false;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user