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[AMDGPU] Set SchedRW on real instructions

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Coyp SchedRW from pseudos to real instructions so that llvm-mca has
access to it. This is NFC for normal compiler codegen, which schedules
pseudos not real instructions.

Add an llvm-mca test for some high latency double-precision instructions
as a smoke test.

Differential Revision: https://reviews.llvm.org/D99187
This commit is contained in:
Jay Foad 2021-03-23 14:02:25 +00:00
parent 32c6d48884
commit abd0bfe722
10 changed files with 221 additions and 20 deletions
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2
lib/Target/AMDGPU/BUFInstructions.td
View File

@ -117,6 +117,7 @@ class MTBUF_Real <MTBUF_Pseudo ps> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
bits<12> offset;
bits<5> cpol;
@ -347,6 +348,7 @@ class MUBUF_Real <MUBUF_Pseudo ps> :
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
bits<12> offset;
bits<5> cpol;

3
lib/Target/AMDGPU/DSInstructions.td
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@ -63,8 +63,9 @@ class DS_Real <DS_Pseudo ds> :
// copy relevant pseudo op flags
let SubtargetPredicate = ds.SubtargetPredicate;
let OtherPredicates = ds.OtherPredicates;
let OtherPredicates = ds.OtherPredicates;
let AsmMatchConverter = ds.AsmMatchConverter;
let SchedRW = ds.SchedRW;
// encoding fields
bits<10> vdst;

9
lib/Target/AMDGPU/FLATInstructions.td
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@ -82,11 +82,12 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let TSFlags = ps.TSFlags;
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
// encoding fields
bits<8> vaddr;

7
lib/Target/AMDGPU/SMInstructions.td
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@ -57,10 +57,11 @@ class SM_Real <SM_Pseudo ps>
Instruction Opcode = !cast<Instruction>(NAME);
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SMRD = ps.SMRD;
let SMRD = ps.SMRD;
let SchedRW = ps.SchedRW;
let TSFlags = ps.TSFlags;

27
lib/Target/AMDGPU/SOPInstructions.td
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@ -66,6 +66,7 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let SchedRW = ps.SchedRW;
// encoding
bits<7> sdst;
@ -369,10 +370,11 @@ class SOP2_Real<bits<7> op, SOP_Pseudo ps, string real_name = ps.Mnemonic> :
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let TSFlags = ps.TSFlags;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
// encoding
bits<7> sdst;
@ -703,6 +705,7 @@ class SOPK_Real<bits<5> op, SOPK_Pseudo ps> :
let AsmMatchConverter = ps.AsmMatchConverter;
let DisableEncoding = ps.DisableEncoding;
let Constraints = ps.Constraints;
let SchedRW = ps.SchedRW;
// encoding
bits<7> sdst;
@ -953,11 +956,12 @@ class SOPC_Real<bits<7> op, SOPC_Pseudo ps, string real_name = ps.Mnemonic> :
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let SubtargetPredicate = ps.SubtargetPredicate;
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let TSFlags = ps.TSFlags;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
// encoding
bits<8> src0;
@ -1081,11 +1085,12 @@ class SOPP_Real<bits<7> op, SOPP_Pseudo ps, string real_name = ps.Mnemonic> :
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let SubtargetPredicate = ps.SubtargetPredicate;
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let TSFlags = ps.TSFlags;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
bits <16> simm16;
}

1
lib/Target/AMDGPU/VOP1Instructions.td
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@ -79,6 +79,7 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
}
class VOP1_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :

1
lib/Target/AMDGPU/VOP2Instructions.td
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@ -101,6 +101,7 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
}
class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :

1
lib/Target/AMDGPU/VOPCInstructions.td
View File

@ -121,6 +121,7 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
}
class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :

5
lib/Target/AMDGPU/VOPInstructions.td
View File

@ -162,6 +162,7 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> :
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
VOPProfile Pfl = ps.Pfl;
}
@ -519,7 +520,6 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
let Defs = ps.Defs;
let Uses = ps.Uses;
let SchedRW = ps.SchedRW;
let hasSideEffects = ps.hasSideEffects;
let Constraints = ps.Constraints;
@ -535,6 +535,7 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
}
class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
@ -563,6 +564,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
}
class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
@ -664,6 +666,7 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
}
class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,

185
test/tools/llvm-mca/AMDGPU/gfx10-double.s Normal file
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@ -0,0 +1,185 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1010 --timeline --iterations=1 < %s | FileCheck %s
v_cvt_i32_f64 v0, v[0:1]
v_cvt_f64_i32 v[2:3], v2
v_cvt_f32_f64 v4, v[4:5]
v_cvt_f64_f32 v[6:7], v6
v_cvt_u32_f64 v8, v[8:9]
v_cvt_f64_u32 v[10:11], v10
v_frexp_exp_i32_f64 v0, v[0:1]
v_frexp_mant_f64 v[2:3], v[2:3]
v_fract_f64 v[4:5], v[4:5]
v_trunc_f64 v[0:1], v[0:1]
v_ceil_f64 v[2:3], v[2:3]
v_rndne_f64 v[4:5], v[4:5]
v_floor_f64 v[6:7], v[6:7]
v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]
v_add_f64 v[2:3], v[2:3], v[2:3]
v_mul_f64 v[4:5], v[4:5], v[4:5]
v_min_f64 v[6:7], v[6:7], v[6:7]
v_max_f64 v[8:9], v[8:9], v[8:9]
v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]
v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]
v_ldexp_f64 v[2:3], v[2:3], v0
; FIXME: This instructions sends llvm-mca into an infinite loop
;v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1]
v_trig_preop_f64 v[2:3], v[2:3], v0
v_cmp_eq_f64 v[0:1], v[0:1]
v_cmp_class_f64 vcc_lo, v[2:3], s0
v_rcp_f64 v[0:1], v[0:1]
v_rsq_f64 v[2:3], v[2:3]
v_sqrt_f64 v[4:5], v[4:5]
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 27
# CHECK-NEXT: Total Cycles: 205
# CHECK-NEXT: Total uOps: 27
# CHECK: Dispatch Width: 1
# CHECK-NEXT: uOps Per Cycle: 0.13
# CHECK-NEXT: IPC: 0.13
# CHECK-NEXT: Block RThroughput: 27.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 22 1.00 U v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: 1 22 1.00 U v_cvt_f32_f64_e32 v4, v[4:5]
# CHECK-NEXT: 1 22 1.00 U v_cvt_f64_f32_e32 v[6:7], v6
# CHECK-NEXT: 1 22 1.00 U v_cvt_u32_f64_e32 v8, v[8:9]
# CHECK-NEXT: 1 22 1.00 U v_cvt_f64_u32_e32 v[10:11], v10
# CHECK-NEXT: 1 22 1.00 U v_frexp_exp_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_frexp_mant_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: 1 22 1.00 U v_fract_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: 1 22 1.00 U v_trunc_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_ceil_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: 1 22 1.00 U v_rndne_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: 1 22 1.00 U v_floor_f64_e32 v[6:7], v[6:7]
# CHECK-NEXT: 1 22 1.00 U v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_add_f64 v[2:3], v[2:3], v[2:3]
# CHECK-NEXT: 1 22 1.00 U v_mul_f64 v[4:5], v[4:5], v[4:5]
# CHECK-NEXT: 1 22 1.00 U v_min_f64 v[6:7], v[6:7], v[6:7]
# CHECK-NEXT: 1 22 1.00 U v_max_f64 v[8:9], v[8:9], v[8:9]
# CHECK-NEXT: 1 22 1.00 U v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_ldexp_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: 1 22 1.00 U v_trig_preop_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: 1 22 1.00 U v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]
# CHECK-NEXT: 1 22 1.00 U v_cmp_class_f64_e64 vcc_lo, v[2:3], s0
# CHECK-NEXT: 1 24 1.00 U v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 1 24 1.00 U v_rsq_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: 1 24 1.00 U v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK: Resources:
# CHECK-NEXT: [0] - HWBranch
# CHECK-NEXT: [1] - HWExport
# CHECK-NEXT: [2] - HWLGKM
# CHECK-NEXT: [3] - HWRC
# CHECK-NEXT: [4] - HWSALU
# CHECK-NEXT: [5] - HWVALU
# CHECK-NEXT: [6] - HWVMEM
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6]
# CHECK-NEXT: - - - 27.00 - 27.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f32_f64_e32 v4, v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f64_f32_e32 v[6:7], v6
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_u32_f64_e32 v8, v[8:9]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cvt_f64_u32_e32 v[10:11], v10
# CHECK-NEXT: - - - 1.00 - 1.00 - v_frexp_exp_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_frexp_mant_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_fract_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_trunc_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_ceil_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_rndne_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_floor_f64_e32 v[6:7], v[6:7]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_add_f64 v[2:3], v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_mul_f64 v[4:5], v[4:5], v[4:5]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_min_f64 v[6:7], v[6:7], v[6:7]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_max_f64 v[8:9], v[8:9], v[8:9]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_ldexp_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: - - - 1.00 - 1.00 - v_trig_preop_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_cmp_class_f64_e64 vcc_lo, v[2:3], s0
# CHECK-NEXT: - - - 1.00 - 1.00 - v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_rsq_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: - - - 1.00 - 1.00 - v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789 0
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . . v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: [0,1] .DeeeeeeeeeeeeeeeeeeeeeER. . . . . . . . . . v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: [0,2] . DeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . v_cvt_f32_f64_e32 v4, v[4:5]
# CHECK-NEXT: [0,3] . DeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . v_cvt_f64_f32_e32 v[6:7], v6
# CHECK-NEXT: [0,4] . DeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . v_cvt_u32_f64_e32 v8, v[8:9]
# CHECK-NEXT: [0,5] . DeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . v_cvt_f64_u32_e32 v[10:11], v10
# CHECK-NEXT: [0,6] . . . . . DeeeeeeeeeeeeeeeeeeeeeER . . . . . v_frexp_exp_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: [0,7] . . . . . DeeeeeeeeeeeeeeeeeeeeeER . . . . . v_frexp_mant_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: [0,8] . . . . . DeeeeeeeeeeeeeeeeeeeeeER . . . . . v_fract_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: [0,9] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeER . v_trunc_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: [0,10] . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeER . v_ceil_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: [0,11] . . . . . . . . . .DeeeeeeeeeeeeeeeeeeeeeER. v_rndne_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: [0,12] . . . . . . . . . . DeeeeeeeeeeeeeeeeeeeeeER v_floor_f64_e32 v[6:7], v[6:7]
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 v_cvt_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 v_cvt_f64_i32_e32 v[2:3], v2
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 v_cvt_f32_f64_e32 v4, v[4:5]
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 v_cvt_f64_f32_e32 v[6:7], v6
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 v_cvt_u32_f64_e32 v8, v[8:9]
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 v_cvt_f64_u32_e32 v[10:11], v10
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 v_frexp_exp_i32_f64_e32 v0, v[0:1]
# CHECK-NEXT: 7. 1 0.0 0.0 0.0 v_frexp_mant_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: 8. 1 0.0 0.0 0.0 v_fract_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: 9. 1 0.0 0.0 0.0 v_trunc_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 10. 1 0.0 0.0 0.0 v_ceil_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: 11. 1 0.0 0.0 0.0 v_rndne_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: 12. 1 0.0 0.0 0.0 v_floor_f64_e32 v[6:7], v[6:7]
# CHECK-NEXT: 13. 1 0.0 0.0 0.0 v_fma_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: 14. 1 0.0 0.0 0.0 v_add_f64 v[2:3], v[2:3], v[2:3]
# CHECK-NEXT: 15. 1 0.0 0.0 0.0 v_mul_f64 v[4:5], v[4:5], v[4:5]
# CHECK-NEXT: 16. 1 0.0 0.0 0.0 v_min_f64 v[6:7], v[6:7], v[6:7]
# CHECK-NEXT: 17. 1 0.0 0.0 0.0 v_max_f64 v[8:9], v[8:9], v[8:9]
# CHECK-NEXT: 18. 1 0.0 0.0 0.0 v_div_fmas_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: 19. 1 0.0 0.0 0.0 v_div_fixup_f64 v[0:1], v[0:1], v[0:1], v[0:1]
# CHECK-NEXT: 20. 1 0.0 0.0 0.0 v_ldexp_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: 21. 1 0.0 0.0 0.0 v_trig_preop_f64 v[2:3], v[2:3], v0
# CHECK-NEXT: 22. 1 0.0 0.0 0.0 v_cmp_eq_f64_e32 vcc_lo, v[0:1], v[0:1]
# CHECK-NEXT: 23. 1 0.0 0.0 0.0 v_cmp_class_f64_e64 vcc_lo, v[2:3], s0
# CHECK-NEXT: 24. 1 0.0 0.0 0.0 v_rcp_f64_e32 v[0:1], v[0:1]
# CHECK-NEXT: 25. 1 0.0 0.0 0.0 v_rsq_f64_e32 v[2:3], v[2:3]
# CHECK-NEXT: 26. 1 0.0 0.0 0.0 v_sqrt_f64_e32 v[4:5], v[4:5]
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>