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[NVPTX] Add selp.f32 checks to select(cond,fpbinop(),fpbinop()) tests
Will help show codegen diffs in an upcoming patch
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@ -149,6 +149,7 @@ define float @repeated_div_recip_allowed(i1 %pred, float %a, float %b, float %di
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; CHECK: rcp.rn.f32
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; CHECK: mul.rn.f32
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; CHECK: mul.rn.f32
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; CHECK: selp.f32
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%x = fdiv arcp float %a, %divisor
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%y = fdiv arcp float %b, %divisor
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%z = select i1 %pred, float %x, float %y
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@ -160,6 +161,7 @@ define float @repeated_div_recip_allowed_ftz(i1 %pred, float %a, float %b, float
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; CHECK: rcp.rn.ftz.f32
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; CHECK: mul.rn.ftz.f32
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; CHECK: mul.rn.ftz.f32
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; CHECK: selp.f32
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%x = fdiv arcp float %a, %divisor
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%y = fdiv arcp float %b, %divisor
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%z = select i1 %pred, float %x, float %y
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@ -171,6 +173,7 @@ define float @repeated_div_fast(i1 %pred, float %a, float %b, float %divisor) #0
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; CHECK: rcp.approx.f32
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; CHECK: mul.f32
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; CHECK: mul.f32
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; CHECK: selp.f32
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%x = fdiv float %a, %divisor
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%y = fdiv float %b, %divisor
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%z = select i1 %pred, float %x, float %y
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@ -182,6 +185,7 @@ define float @repeated_div_fast_ftz(i1 %pred, float %a, float %b, float %divisor
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; CHECK: rcp.approx.ftz.f32
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; CHECK: mul.ftz.f32
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; CHECK: mul.ftz.f32
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; CHECK: selp.f32
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%x = fdiv float %a, %divisor
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%y = fdiv float %b, %divisor
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%z = select i1 %pred, float %x, float %y
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