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[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values
We allocated a suitably aligned frame index so we know that all the values have ABI alignment. For MIPS this avoids using pair of lwl + lwr instructions instead of a single lw. I found this when compiling CHERI pure capability code where we can't use the lwl/lwr unaligned loads/stores and and were to falling back to a byte load + shift + or sequence. This should save a few instructions for MIPS and possibly other backends that don't have fast unaligned loads/stores. It also improves code generation for CodeGen/X86/pr34653.ll and CodeGen/WebAssembly/offset.ll since they can now use aligned loads. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D78999
This commit is contained in:
Alex Richardson
parent
283e2844aa
commit
ac2e4676eb
@ -1833,6 +1833,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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unsigned NumValues = ValueVTs.size();
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SmallVector<SDValue, 4> Chains(NumValues);
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Align BaseAlign = DL.getPrefTypeAlign(I.getOperand(0)->getType());
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for (unsigned i = 0; i != NumValues; ++i) {
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// An aggregate return value cannot wrap around the address space, so
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// offsets to its parts don't wrap either.
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@ -1841,9 +1842,11 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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SDValue Val = RetOp.getValue(RetOp.getResNo() + i);
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if (MemVTs[i] != ValueVTs[i])
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Val = DAG.getPtrExtOrTrunc(Val, getCurSDLoc(), MemVTs[i]);
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Chains[i] = DAG.getStore(Chain, getCurSDLoc(), Val,
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Chains[i] = DAG.getStore(
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Chain, getCurSDLoc(), Val,
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// FIXME: better loc info would be nice.
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Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()));
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Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()),
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commonAlignment(BaseAlign, Offsets[i]));
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}
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Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
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@ -9271,6 +9274,8 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(true);
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MachineFunction &MF = CLI.DAG.getMachineFunction();
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Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx);
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for (unsigned i = 0; i < NumValues; ++i) {
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SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
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CLI.DAG.getConstant(Offsets[i], CLI.DL,
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@ -9279,7 +9284,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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RetTys[i], CLI.DL, CLI.Chain, Add,
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MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
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DemoteStackIdx, Offsets[i]),
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/* Alignment = */ 1);
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HiddenSRetAlign);
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ReturnValues[i] = L;
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Chains[i] = L.getValue(1);
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}
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@ -16,23 +16,13 @@ define internal void @test() unnamed_addr nounwind {
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; CHECK-NEXT: daddiu $4, $sp, 8
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; CHECK-NEXT: jal implicit_sret_decl
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; CHECK-NEXT: nop
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; CHECK-NEXT: # implicit-def: $at_64
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; CHECK-NEXT: ldl $1, 24($sp)
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; CHECK-NEXT: ldr $1, 31($sp)
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; CHECK-NEXT: ld $6, 24($sp)
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; CHECK-NEXT: ld $5, 16($sp)
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; CHECK-NEXT: ld $7, 32($sp)
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; CHECK-NEXT: lw $1, 8($sp)
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; CHECK-NEXT: # implicit-def: $v0_64
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; CHECK-NEXT: ldl $2, 16($sp)
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; CHECK-NEXT: ldr $2, 23($sp)
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; CHECK-NEXT: # implicit-def: $v1_64
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; CHECK-NEXT: ldl $3, 32($sp)
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; CHECK-NEXT: ldr $3, 39($sp)
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; CHECK-NEXT: # implicit-def: $a1
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; CHECK-NEXT: lwl $5, 8($sp)
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; CHECK-NEXT: lwr $5, 11($sp)
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; CHECK-NEXT: # implicit-def: $a0_64
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; CHECK-NEXT: move $4, $5
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; CHECK-NEXT: move $5, $2
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; CHECK-NEXT: move $6, $1
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; CHECK-NEXT: move $7, $3
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; CHECK-NEXT: move $2, $1
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; CHECK-NEXT: move $4, $2
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; CHECK-NEXT: jal use_sret
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; CHECK-NEXT: nop
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; CHECK-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload
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@ -75,15 +65,9 @@ define internal void @test2() unnamed_addr nounwind {
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; CHECK-NEXT: daddiu $4, $sp, 0
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; CHECK-NEXT: jal implicit_sret_decl2
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; CHECK-NEXT: nop
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; CHECK-NEXT: # implicit-def: $at
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; CHECK-NEXT: lwl $1, 20($sp)
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; CHECK-NEXT: lwr $1, 23($sp)
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; CHECK-NEXT: # implicit-def: $v0
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; CHECK-NEXT: lwl $2, 12($sp)
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; CHECK-NEXT: lwr $2, 15($sp)
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; CHECK-NEXT: # implicit-def: $v1
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; CHECK-NEXT: lwl $3, 4($sp)
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; CHECK-NEXT: lwr $3, 7($sp)
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; CHECK-NEXT: lw $1, 20($sp)
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; CHECK-NEXT: lw $2, 12($sp)
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; CHECK-NEXT: lw $3, 4($sp)
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; CHECK-NEXT: # implicit-def: $a0_64
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; CHECK-NEXT: move $4, $3
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; CHECK-NEXT: # implicit-def: $a1_64
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@ -645,9 +645,9 @@ define void @aggregate_load_store({i32,i32,i32,i32}* %p, {i32,i32,i32,i32}* %q)
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; CHECK-LABEL: aggregate_return:
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; CHECK: i64.const $push[[L0:[0-9]+]]=, 0{{$}}
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; CHECK: i64.store 8($0):p2align=2, $pop[[L0]]{{$}}
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; CHECK: i64.store 8($0), $pop[[L0]]{{$}}
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; CHECK: i64.const $push[[L1:[0-9]+]]=, 0{{$}}
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; CHECK: i64.store 0($0):p2align=2, $pop[[L1]]{{$}}
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; CHECK: i64.store 0($0), $pop[[L1]]{{$}}
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define {i32,i32,i32,i32} @aggregate_return() {
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ret {i32,i32,i32,i32} zeroinitializer
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}
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@ -15,28 +15,22 @@ define void @pr34653() {
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; CHECK-NEXT: subq $1536, %rsp # imm = 0x600
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; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
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; CHECK-NEXT: callq test
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm1
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm2
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm3
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm4
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm5
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm6
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm7
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm8
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm9
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm10
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm11
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm12
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm13
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm14
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm15
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovupd {{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm4 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm5 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm6 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm7 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm8 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm9 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm10 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm11 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm12 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm13 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm14 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm15 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm16 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm17 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm18 = mem[0],zero
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@ -60,17 +54,11 @@ define void @pr34653() {
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
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; CHECK-NEXT: # xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
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; CHECK-NEXT: # xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
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; CHECK-NEXT: # xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
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; CHECK-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
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; CHECK-NEXT: # xmm0 = mem[0],zero
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; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: movq %rbp, %rsp
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa %rsp, 8
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