RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 20:12:56 +02:00
Code Issues Projects Releases Wiki Activity

[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions.

Browse Source 
The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

llvm-svn: 214499
This commit is contained in:
Tilmann Scheller 2014-08-01 11:33:47 +00:00
parent 4926154eef
commit ac50eef593
2 changed files with 37 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5750,7 +5750,11 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::LDR_PRE_IMM:
case ARM::LDR_PRE_REG:
case ARM::LDR_POST_IMM:
case ARM::LDR_POST_REG: {
case ARM::LDR_POST_REG:
case ARM::LDRH_PRE:
case ARM::LDRH_POST:
case ARM::LDRSH_PRE:
case ARM::LDRSH_POST: {
// Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());

32
test/MC/ARM/diagnostics.s
View File

@ -545,6 +545,14 @@ foo2:
ldr r0, [r0, r1]!
ldr r0, [r0], #4
ldr r0, [r0], r1
ldrh r0, [r0, #2]!
ldrh r0, [r0, r1]!
ldrh r0, [r0], #2
ldrh r0, [r0], r1
ldrsh r0, [r0, #2]!
ldrsh r0, [r0, r1]!
ldrsh r0, [r0], #2
ldrsh r0, [r0], r1
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ -557,3 +565,27 @@ foo2:
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0, #2]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0], #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0, #2]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0], #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0], r1
@ CHECK-ERRORS: ^