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[LoopUnroll] Regenerate test checks (NFC)
This commit is contained in:
Nikita Popov
parent
cdf04cd5e0
commit
ac5625799c
@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -indvars -loop-unroll -verify-loop-info | FileCheck %s
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;
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; Unit tests for loop unrolling using ScalarEvolution to compute trip counts.
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@ -6,12 +7,41 @@
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; tests may check that SCEV is properly invalidated between passes.
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; Completely unroll loops without a canonical IV.
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;
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; CHECK-LABEL: @sansCanonical(
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; CHECK-NOT: phi
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; CHECK-NOT: icmp
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; CHECK: ret
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define i32 @sansCanonical(i32* %base) nounwind {
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; CHECK-LABEL: @sansCanonical(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 0 to i64
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; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[ADR:%.*]] = getelementptr inbounds i32, i32* [[BASE:%.*]], i64 9
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; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[ADR]], align 8
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; CHECK-NEXT: [[ADR_1:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 8
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; CHECK-NEXT: [[TMP_1:%.*]] = load i32, i32* [[ADR_1]], align 8
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; CHECK-NEXT: [[SUM_NEXT_1:%.*]] = add i32 [[TMP]], [[TMP_1]]
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; CHECK-NEXT: [[ADR_2:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 7
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; CHECK-NEXT: [[TMP_2:%.*]] = load i32, i32* [[ADR_2]], align 8
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; CHECK-NEXT: [[SUM_NEXT_2:%.*]] = add i32 [[SUM_NEXT_1]], [[TMP_2]]
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; CHECK-NEXT: [[ADR_3:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 6
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; CHECK-NEXT: [[TMP_3:%.*]] = load i32, i32* [[ADR_3]], align 8
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; CHECK-NEXT: [[SUM_NEXT_3:%.*]] = add i32 [[SUM_NEXT_2]], [[TMP_3]]
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; CHECK-NEXT: [[ADR_4:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 5
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; CHECK-NEXT: [[TMP_4:%.*]] = load i32, i32* [[ADR_4]], align 8
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; CHECK-NEXT: [[SUM_NEXT_4:%.*]] = add i32 [[SUM_NEXT_3]], [[TMP_4]]
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; CHECK-NEXT: [[ADR_5:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 4
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; CHECK-NEXT: [[TMP_5:%.*]] = load i32, i32* [[ADR_5]], align 8
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; CHECK-NEXT: [[SUM_NEXT_5:%.*]] = add i32 [[SUM_NEXT_4]], [[TMP_5]]
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; CHECK-NEXT: [[ADR_6:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 3
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; CHECK-NEXT: [[TMP_6:%.*]] = load i32, i32* [[ADR_6]], align 8
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; CHECK-NEXT: [[SUM_NEXT_6:%.*]] = add i32 [[SUM_NEXT_5]], [[TMP_6]]
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; CHECK-NEXT: [[ADR_7:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 2
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; CHECK-NEXT: [[TMP_7:%.*]] = load i32, i32* [[ADR_7]], align 8
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; CHECK-NEXT: [[SUM_NEXT_7:%.*]] = add i32 [[SUM_NEXT_6]], [[TMP_7]]
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; CHECK-NEXT: [[ADR_8:%.*]] = getelementptr inbounds i32, i32* [[BASE]], i64 1
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; CHECK-NEXT: [[TMP_8:%.*]] = load i32, i32* [[ADR_8]], align 8
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; CHECK-NEXT: [[SUM_NEXT_8:%.*]] = add i32 [[SUM_NEXT_7]], [[TMP_8]]
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; CHECK-NEXT: [[TMP_9:%.*]] = load i32, i32* [[BASE]], align 8
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; CHECK-NEXT: ret i32 [[SUM_NEXT_8]]
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;
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entry:
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br label %while.body
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@ -34,12 +64,29 @@ exit:
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; case, the computed trip count based on a canonical IV is *not* for a
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; latch block. Canonical unrolling incorrectly unrolls it, but SCEV
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; unrolling does not.
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;
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; CHECK-LABEL: @earlyLoopTest(
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; CHECK: tail:
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; CHECK-NOT: br
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; CHECK: br i1 %cmp2, label %loop, label %exit2
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define i64 @earlyLoopTest(i64* %base) nounwind {
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; CHECK-LABEL: @earlyLoopTest(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[TAIL:%.*]] ]
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; CHECK-NEXT: [[S:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[S_NEXT:%.*]], [[TAIL]] ]
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; CHECK-NEXT: [[ADR:%.*]] = getelementptr i64, i64* [[BASE:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[VAL:%.*]] = load i64, i64* [[ADR]], align 4
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; CHECK-NEXT: [[S_NEXT]] = add i64 [[S]], [[VAL]]
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; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[INC]], 4
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; CHECK-NEXT: br i1 [[CMP]], label [[TAIL]], label [[EXIT1:%.*]]
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; CHECK: tail:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i64 [[VAL]], 0
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: [[S_LCSSA:%.*]] = phi i64 [ [[S]], [[LOOP]] ]
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; CHECK-NEXT: ret i64 [[S_LCSSA]]
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; CHECK: exit2:
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; CHECK-NEXT: [[S_NEXT_LCSSA1:%.*]] = phi i64 [ [[S_NEXT]], [[TAIL]] ]
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; CHECK-NEXT: ret i64 [[S_NEXT_LCSSA1]]
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;
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entry:
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br label %loop
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@ -65,13 +112,24 @@ exit2:
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}
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; SCEV properly unrolls multi-exit loops.
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;
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; CHECK-LABEL: @multiExit(
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; CHECK: getelementptr i32, i32* %base, i32 %iv
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; CHECK-NEXT: load i32, i32*
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; CHECK: br i1 false, label %l2, label %exit1
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; CHECK: br i1 true, label %l1, label %exit2
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define i32 @multiExit(i32* %base) nounwind {
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; CHECK-LABEL: @multiExit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[L1:%.*]]
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; CHECK: l1:
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; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[L2:%.*]] ]
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; CHECK-NEXT: [[INC1]] = add nuw nsw i32 [[IV1]], 1
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; CHECK-NEXT: [[ADR:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i32 [[IV1]]
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
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; CHECK-NEXT: br i1 false, label [[L2]], label [[EXIT1:%.*]]
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; CHECK: l2:
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; CHECK-NEXT: br i1 true, label [[L1]], label [[EXIT2:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: ret i32 1
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; CHECK: exit2:
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; CHECK-NEXT: [[VAL_LCSSA1:%.*]] = phi i32 [ [[VAL]], [[L2]] ]
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; CHECK-NEXT: ret i32 [[VAL_LCSSA1]]
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;
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entry:
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br label %l1
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l1:
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@ -97,12 +155,29 @@ exit2:
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; a known trip count, regardless of the early exit trip counts. The
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; LoopUnroll utility uses this assumption to optimize the latch
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; block's branch.
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;
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; CHECK-LABEL: @multiExitIncomplete(
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; CHECK: l3:
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; CHECK-NOT: br
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; CHECK: br i1 %cmp3, label %l1, label %exit3
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define i32 @multiExitIncomplete(i32* %base) nounwind {
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; CHECK-LABEL: @multiExitIncomplete(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[L1:%.*]]
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; CHECK: l1:
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; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC1:%.*]], [[L3:%.*]] ]
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; CHECK-NEXT: [[INC1]] = add nuw i32 [[IV1]], 1
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; CHECK-NEXT: [[ADR:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i32 [[IV1]]
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; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[ADR]], align 4
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IV1]], 5
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; CHECK-NEXT: br i1 [[CMP1]], label [[L2:%.*]], label [[EXIT1:%.*]]
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; CHECK: l2:
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; CHECK-NEXT: br i1 true, label [[L3]], label [[EXIT2:%.*]]
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; CHECK: l3:
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; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[VAL]], 0
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; CHECK-NEXT: br i1 [[CMP3]], label [[L1]], label [[EXIT3:%.*]]
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; CHECK: exit1:
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; CHECK-NEXT: ret i32 1
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; CHECK: exit2:
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; CHECK-NEXT: ret i32 2
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; CHECK: exit3:
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; CHECK-NEXT: ret i32 3
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;
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entry:
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br label %l1
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l1:
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@ -131,11 +206,19 @@ exit3:
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; When loop unroll merges a loop exit with one of its parent loop's
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; exits, SCEV must forget its ExitNotTaken info.
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;
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; CHECK-LABEL: @nestedUnroll(
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; CHECK-NOT: br i1
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; CHECK: for.body87:
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define void @nestedUnroll() nounwind {
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; CHECK-LABEL: @nestedUnroll(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_INC:%.*]]
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; CHECK: for.inc:
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; CHECK-NEXT: br label [[FOR_BODY38:%.*]]
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; CHECK: for.body38:
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; CHECK-NEXT: br label [[FOR_BODY43:%.*]]
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; CHECK: for.body43:
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; CHECK-NEXT: br label [[FOR_BODY87:%.*]]
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; CHECK: for.body87:
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; CHECK-NEXT: br label [[FOR_BODY87]]
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;
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entry:
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br label %for.inc
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@ -177,13 +260,23 @@ for.body87:
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; iteration via the early exit. So loop unrolling cannot assume that
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; the loop latch's exit count of zero is an upper bound on the number
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; of iterations.
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;
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; CHECK-LABEL: @nsw_latch(
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; CHECK: for.body:
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; CHECK: %b.03 = phi i32 [ 0, %entry ], [ %add, %for.cond ]
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; CHECK: return:
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; CHECK: %b.03.lcssa = phi i32 [ 8, %for.body ], [ 0, %for.cond ]
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define void @nsw_latch(i32* %a) nounwind {
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; CHECK-LABEL: @nsw_latch(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[B_03:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_COND:%.*]] ]
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[B_03]], 0
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; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[B_03]], 8
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; CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_COND]], label [[RETURN:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: br i1 false, label [[RETURN]], label [[FOR_BODY]]
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; CHECK: return:
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; CHECK-NEXT: [[B_03_LCSSA:%.*]] = phi i32 [ 8, [[FOR_BODY]] ], [ 0, [[FOR_COND]] ]
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 1, [[FOR_BODY]] ], [ 0, [[FOR_COND]] ]
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; CHECK-NEXT: store i32 [[B_03_LCSSA]], i32* [[A:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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