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[M68k] Add more specific operand classes
This change adds an operand class for each addressing mode, which can then be used as part of the assembler to match instructions. Differential Revision: https://reviews.llvm.org/D98535
This commit is contained in:
Ricky Taylor
Min-Yih Hsu
parent
eae33fdf31
commit
ad0007c85e
@ -206,14 +206,14 @@ def MxARD32 : MxRegOp<i32, AR32, MxSize32, "a">;
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def MxARD16_TC : MxRegOp<i16, AR16_TC, MxSize16, "a">;
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def MxARD32_TC : MxRegOp<i32, AR32_TC, MxSize32, "a">;
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// TODO finish parser wiring
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def MxMemAsmOperand : AsmOperandClass {
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let Name = "MxMemOp";
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class MxOpClass<string name> : AsmOperandClass {
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let Name = name;
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let ParserMethod = "parse"#name;
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}
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class MxMemOp<dag ops, MxSize size, string letter,
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string printMethod = "printOperand",
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AsmOperandClass parserMatchClass = MxMemAsmOperand>
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AsmOperandClass parserMatchClass = ImmAsmOperand>
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: Operand<iPTR>, MxOperand<iPTR, size, letter, ?> {
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let PrintMethod = printMethod;
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let MIOperandInfo = ops;
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@ -225,13 +225,14 @@ class MxMemOp<dag ops, MxSize size, string letter,
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// register specified by the register field. The reference is classified as
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// a data reference with the exception of the jump and jump-to-subroutine
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// instructions.
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def MxARI8 : MxMemOp<(ops AR32), MxSize8, "j", "printARI8Mem">;
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def MxARI16 : MxMemOp<(ops AR32), MxSize16, "j", "printARI16Mem">;
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def MxARI32 : MxMemOp<(ops AR32), MxSize32, "j", "printARI32Mem">;
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def MxARI : MxOpClass<"ARI">;
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def MxARI8 : MxMemOp<(ops AR32), MxSize8, "j", "printARI8Mem", MxARI>;
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def MxARI16 : MxMemOp<(ops AR32), MxSize16, "j", "printARI16Mem", MxARI>;
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def MxARI32 : MxMemOp<(ops AR32), MxSize32, "j", "printARI32Mem", MxARI>;
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def MxARI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "j", "printARI8Mem">;
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def MxARI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "j", "printARI16Mem">;
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def MxARI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "j", "printARI32Mem">;
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def MxARI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "j", "printARI8Mem", MxARI>;
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def MxARI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "j", "printARI16Mem", MxARI>;
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def MxARI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "j", "printARI32Mem", MxARI>;
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// ADDRESS REGISTER INDIRECT WITH POSTINCREMENT. The address of the operand is
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// in the address register specified by the register field. After the operand
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@ -240,13 +241,14 @@ def MxARI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "j", "printARI32Mem">;
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// is the stack pointer and the operand size is byte, the address is incremented
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// by two rather than one to keep the stack pointer on a word boundary.
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// The reference is classified as a data reference.
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def MxARIPI8 : MxMemOp<(ops AR32), MxSize8, "o", "printARIPI8Mem">;
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def MxARIPI16 : MxMemOp<(ops AR32), MxSize16, "o", "printARIPI16Mem">;
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def MxARIPI32 : MxMemOp<(ops AR32), MxSize32, "o", "printARIPI32Mem">;
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def MxARIPI : MxOpClass<"ARIPI">;
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def MxARIPI8 : MxMemOp<(ops AR32), MxSize8, "o", "printARIPI8Mem", MxARIPI>;
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def MxARIPI16 : MxMemOp<(ops AR32), MxSize16, "o", "printARIPI16Mem", MxARIPI>;
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def MxARIPI32 : MxMemOp<(ops AR32), MxSize32, "o", "printARIPI32Mem", MxARIPI>;
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def MxARIPI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "o", "printARIPI8Mem">;
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def MxARIPI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "o", "printARIPI16Mem">;
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def MxARIPI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "o", "printARIPI32Mem">;
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def MxARIPI8_TC : MxMemOp<(ops AR32_TC), MxSize8, "o", "printARIPI8Mem", MxARIPI>;
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def MxARIPI16_TC : MxMemOp<(ops AR32_TC), MxSize16, "o", "printARIPI16Mem", MxARIPI>;
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def MxARIPI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "o", "printARIPI32Mem", MxARIPI>;
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// ADDRESS REGISTER INDIRECT WITH PREDECREMENT. The address of the operand is in
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// the address register specified by the register field. Before the operand
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@ -255,26 +257,28 @@ def MxARIPI32_TC : MxMemOp<(ops AR32_TC), MxSize32, "o", "printARIPI32Mem">;
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// the stack pointer and the operand size is byte, the address is decremented by
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// two rather than one to keep the stack pointer on a word boundary.
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// The reference is classified as a data reference.
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def MxARIPD8 : MxMemOp<(ops AR32), MxSize8, "e", "printARIPD8Mem">;
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def MxARIPD16 : MxMemOp<(ops AR32), MxSize16, "e", "printARIPD16Mem">;
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def MxARIPD32 : MxMemOp<(ops AR32), MxSize32, "e", "printARIPD32Mem">;
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def MxARIPD : MxOpClass<"ARIPD">;
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def MxARIPD8 : MxMemOp<(ops AR32), MxSize8, "e", "printARIPD8Mem", MxARIPD>;
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def MxARIPD16 : MxMemOp<(ops AR32), MxSize16, "e", "printARIPD16Mem", MxARIPD>;
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def MxARIPD32 : MxMemOp<(ops AR32), MxSize32, "e", "printARIPD32Mem", MxARIPD>;
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def MxARIPD8_TC : MxMemOp<(ops AR32_TC), MxSize8, "e", "printARIPD8Mem">;
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def MxARIPD16_TC : MxMemOp<(ops AR32_TC), MxSize16, "e", "printARIPD16Mem">;
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def MxARIPD32_TC : MxMemOp<(ops AR32_TC), MxSize32, "e", "printARIPD32Mem">;
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def MxARIPD8_TC : MxMemOp<(ops AR32_TC), MxSize8, "e", "printARIPD8Mem", MxARIPD>;
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def MxARIPD16_TC : MxMemOp<(ops AR32_TC), MxSize16, "e", "printARIPD16Mem", MxARIPD>;
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def MxARIPD32_TC : MxMemOp<(ops AR32_TC), MxSize32, "e", "printARIPD32Mem", MxARIPD>;
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// ADDRESS REGISTER INDIRECT WITH DISPLACEMENT. This addressing mode requires one
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// word of extension. The address of the operand is the sum of the address in
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// the address register and the sign-extended 16-bit displacement integer in the
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// extension word. The reference is classified as a data reference with the
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// exception of the jump and jump-to-subroutine instructions.
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def MxARID8 : MxMemOp<(ops i16imm, AR32), MxSize8, "p", "printARID8Mem">;
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def MxARID16 : MxMemOp<(ops i16imm, AR32), MxSize16, "p", "printARID16Mem">;
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def MxARID32 : MxMemOp<(ops i16imm, AR32), MxSize32, "p", "printARID32Mem">;
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def MxARID : MxOpClass<"ARID">;
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def MxARID8 : MxMemOp<(ops i16imm, AR32), MxSize8, "p", "printARID8Mem", MxARID>;
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def MxARID16 : MxMemOp<(ops i16imm, AR32), MxSize16, "p", "printARID16Mem", MxARID>;
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def MxARID32 : MxMemOp<(ops i16imm, AR32), MxSize32, "p", "printARID32Mem", MxARID>;
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def MxARID8_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize8, "p", "printARID8Mem">;
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def MxARID16_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize16, "p", "printARID16Mem">;
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def MxARID32_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize32, "p", "printARID32Mem">;
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def MxARID8_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize8, "p", "printARID8Mem", MxARID>;
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def MxARID16_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize16, "p", "printARID16Mem", MxARID>;
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def MxARID32_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize32, "p", "printARID32Mem", MxARID>;
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// ADDRESS REGISTER INDIRECT WITH INDEX. This addressing mode requires one word
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// of extension. The address of the operand is the sum of the address in the
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@ -282,21 +286,23 @@ def MxARID32_TC : MxMemOp<(ops i16imm, AR32_TC), MxSize32, "p", "printARID32Me
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// bits of the extension word, and the contents of the index register.
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// The reference is classified as a data reference with the exception of the
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// jump and jump-to-subroutine instructions
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def MxARII8 : MxMemOp<(ops i8imm, AR32, XR32), MxSize8, "f", "printARII8Mem">;
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def MxARII16 : MxMemOp<(ops i8imm, AR32, XR32), MxSize16, "f", "printARII16Mem">;
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def MxARII32 : MxMemOp<(ops i8imm, AR32, XR32), MxSize32, "f", "printARII32Mem">;
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def MxARII : MxOpClass<"ARII">;
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def MxARII8 : MxMemOp<(ops i8imm, AR32, XR32), MxSize8, "f", "printARII8Mem", MxARII>;
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def MxARII16 : MxMemOp<(ops i8imm, AR32, XR32), MxSize16, "f", "printARII16Mem", MxARII>;
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def MxARII32 : MxMemOp<(ops i8imm, AR32, XR32), MxSize32, "f", "printARII32Mem", MxARII>;
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def MxARII8_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize8, "f", "printARII8Mem">;
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def MxARII16_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize16, "f", "printARII16Mem">;
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def MxARII32_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize32, "f", "printARII32Mem">;
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def MxARII8_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize8, "f", "printARII8Mem", MxARII>;
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def MxARII16_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize16, "f", "printARII16Mem", MxARII>;
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def MxARII32_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize32, "f", "printARII32Mem", MxARII>;
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// ABSOLUTE SHORT ADDRESS. This addressing mode requires one word of extension.
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// The address of the operand is the extension word. The 16-bit address is sign
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// extended before it is used. The reference is classified as a data reference
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// with the exception of the jump and jump-tosubroutine instructions.
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def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem">;
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def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem">;
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def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem">;
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def MxAddr : MxOpClass<"Addr">;
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def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem", MxAddr>;
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def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem", MxAddr>;
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def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem", MxAddr>;
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// ABSOLUTE LONG ADDRESS. This addressing mode requires two words of extension.
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// The address of the operand is developed by the concatenation of the extension
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@ -304,9 +310,12 @@ def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem">;
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// order part of the address is the second extension word. The reference is
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// classified as a data reference with the exception of the jump and jump
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// to-subroutine instructions.
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def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem">;
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def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem">;
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def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem">;
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def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem", MxAddr>;
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def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem", MxAddr>;
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def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem", MxAddr>;
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def MxPCD : MxOpClass<"PCD">;
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def MxPCI : MxOpClass<"PCI">;
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let OperandType = "OPERAND_PCREL" in {
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// PROGRAM COUNTER WITH DISPLACEMENT. This addressing mode requires one word of
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@ -314,9 +323,9 @@ let OperandType = "OPERAND_PCREL" in {
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// counter and the Sign-extended 16-bit displacement integer in the extension
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// word. The value in the program counter is the address of the extension word.
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// The reference is classified as a program reference.
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def MxPCD8 : MxMemOp<(ops i16imm), MxSize8, "q", "printPCD8Mem">;
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def MxPCD16 : MxMemOp<(ops i16imm), MxSize16, "q", "printPCD16Mem">;
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def MxPCD32 : MxMemOp<(ops i16imm), MxSize32, "q", "printPCD32Mem">;
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def MxPCD8 : MxMemOp<(ops i16imm), MxSize8, "q", "printPCD8Mem", MxPCD>;
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def MxPCD16 : MxMemOp<(ops i16imm), MxSize16, "q", "printPCD16Mem", MxPCD>;
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def MxPCD32 : MxMemOp<(ops i16imm), MxSize32, "q", "printPCD32Mem", MxPCD>;
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// PROGRAM COUNTER WITH INDEX. This addressing mode requires one word of
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// extension. The address is the sum of the address in the program counter, the
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@ -324,14 +333,18 @@ def MxPCD32 : MxMemOp<(ops i16imm), MxSize32, "q", "printPCD32Mem">;
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// word, and the contents of the index register. The value in the program
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// counter is the address of the extension word. This reference is classified as
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// a program reference.
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def MxPCI8 : MxMemOp<(ops i8imm, XR32), MxSize8, "k", "printPCI8Mem">;
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def MxPCI16 : MxMemOp<(ops i8imm, XR32), MxSize16, "k", "printPCI16Mem">;
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def MxPCI32 : MxMemOp<(ops i8imm, XR32), MxSize32, "k", "printPCI32Mem">;
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def MxPCI8 : MxMemOp<(ops i8imm, XR32), MxSize8, "k", "printPCI8Mem", MxPCI>;
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def MxPCI16 : MxMemOp<(ops i8imm, XR32), MxSize16, "k", "printPCI16Mem", MxPCI>;
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def MxPCI32 : MxMemOp<(ops i8imm, XR32), MxSize32, "k", "printPCI32Mem", MxPCI>;
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} // OPERAND_PCREL
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def MxImm : MxOpClass<"MxImm">;
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class MxOp<ValueType vt, MxSize size, string letter>
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: Operand<vt>,
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MxOperand<vt, size, letter, ?>;
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MxOperand<vt, size, letter, ?> {
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let ParserMatchClass = MxImm;
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}
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let OperandType = "OPERAND_IMMEDIATE",
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PrintMethod = "printImmediate" in {
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@ -349,6 +362,7 @@ def Mxi32imm : MxOp<i32, MxSize32, "i">;
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} // OPERAND_IMMEDIATE
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let OperandType = "OPERAND_PCREL",
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ParserMatchClass = MxImm,
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PrintMethod = "printPCRelImm" in {
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// Branch targets have OtherVT type and print as pc-relative values.
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