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[PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments.
Previously, the vins*vlx instructions were incorrectly defined with i64 as the second argument. This patches fixes this issue by correcting the second argument of the vins*vlx instructions/intrinsics to be i32. Differential Revision: https://reviews.llvm.org/D84277
This commit is contained in:
Amy Kwan
parent
e56997e917
commit
ad195760b5
@ -500,27 +500,27 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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[IntrNoMem]>;
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def int_ppc_altivec_vinsbvlx : GCCBuiltin<"__builtin_altivec_vinsbvlx">,
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinsbvrx : GCCBuiltin<"__builtin_altivec_vinsbvrx">,
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinshvlx : GCCBuiltin<"__builtin_altivec_vinshvlx">,
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">,
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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// P10 Vector Insert with immediate.
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def int_ppc_altivec_vinsw :
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@ -245,7 +245,7 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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// VX-Form: [PO VRT RA VRB XO].
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// Destructive (insert) forms are suffixed with _ins.
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class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
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: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, vrrc:$vB),
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: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB),
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!strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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@ -836,32 +836,32 @@ let Predicates = [IsISA3_1] in {
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def VINSBVLX :
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VXForm_VTB5_RA5_ins<15, "vinsbvlx",
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[(set v16i8:$vD,
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(int_ppc_altivec_vinsbvlx v16i8:$vDi, i64:$rA,
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(int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA,
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v16i8:$vB))]>;
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def VINSBVRX :
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VXForm_VTB5_RA5_ins<271, "vinsbvrx",
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[(set v16i8:$vD,
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(int_ppc_altivec_vinsbvrx v16i8:$vDi, i64:$rA,
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(int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA,
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v16i8:$vB))]>;
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def VINSHVLX :
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VXForm_VTB5_RA5_ins<79, "vinshvlx",
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[(set v8i16:$vD,
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(int_ppc_altivec_vinshvlx v8i16:$vDi, i64:$rA,
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(int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA,
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v8i16:$vB))]>;
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def VINSHVRX :
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VXForm_VTB5_RA5_ins<335, "vinshvrx",
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[(set v8i16:$vD,
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(int_ppc_altivec_vinshvrx v8i16:$vDi, i64:$rA,
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(int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA,
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v8i16:$vB))]>;
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def VINSWVLX :
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VXForm_VTB5_RA5_ins<143, "vinswvlx",
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[(set v4i32:$vD,
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(int_ppc_altivec_vinswvlx v4i32:$vDi, i64:$rA,
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(int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA,
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v4i32:$vB))]>;
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def VINSWVRX :
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VXForm_VTB5_RA5_ins<399, "vinswvrx",
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[(set v4i32:$vD,
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(int_ppc_altivec_vinswvrx v4i32:$vDi, i64:$rA,
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(int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA,
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v4i32:$vB))]>;
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def VINSBLX :
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VXForm_VRT5_RAB5_ins<527, "vinsblx",
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@ -170,67 +170,67 @@ entry:
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}
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declare <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64>, i64, i64)
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define <16 x i8> @testVINSBVLX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
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define <16 x i8> @testVINSBVLX(<16 x i8> %a, i32 %b, <16 x i8> %c) {
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; CHECK-LABEL: testVINSBVLX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsbvlx v2, r5, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i64 %b, <16 x i8> %c)
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i32 %b, <16 x i8> %c)
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ret <16 x i8> %0
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}
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declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i64, <16 x i8>)
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declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i32, <16 x i8>)
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define <16 x i8> @testVINSBVRX(<16 x i8> %a, i64 %b, <16 x i8> %c) {
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define <16 x i8> @testVINSBVRX(<16 x i8> %a, i32 %b, <16 x i8> %c) {
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; CHECK-LABEL: testVINSBVRX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinsbvrx v2, r5, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i64 %b, <16 x i8> %c)
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i32 %b, <16 x i8> %c)
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ret <16 x i8> %0
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}
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declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i64, <16 x i8>)
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declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i32, <16 x i8>)
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define <8 x i16> @testVINSHVLX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
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define <8 x i16> @testVINSHVLX(<8 x i16> %a, i32 %b, <8 x i16> %c) {
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; CHECK-LABEL: testVINSHVLX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinshvlx v2, r5, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i64 %b, <8 x i16> %c)
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i32 %b, <8 x i16> %c)
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ret <8 x i16> %0
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}
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declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i64, <8 x i16>)
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declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i32, <8 x i16>)
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define <8 x i16> @testVINSHVRX(<8 x i16> %a, i64 %b, <8 x i16> %c) {
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define <8 x i16> @testVINSHVRX(<8 x i16> %a, i32 %b, <8 x i16> %c) {
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i64 %b, <8 x i16> %c)
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i32 %b, <8 x i16> %c)
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ret <8 x i16> %0
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}
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declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i64, <8 x i16>)
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declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i32, <8 x i16>)
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define <4 x i32> @testVINSWVLX(<4 x i32> %a, i64 %b, <4 x i32> %c) {
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define <4 x i32> @testVINSWVLX(<4 x i32> %a, i32 %b, <4 x i32> %c) {
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; CHECK-LABEL: testVINSWVLX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinswvlx v2, r5, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i64 %b, <4 x i32> %c)
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i32 %b, <4 x i32> %c)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i64, <4 x i32>)
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declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i32, <4 x i32>)
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define <4 x i32> @testVINSWVRX(<4 x i32> %a, i64 %b, <4 x i32> %c) {
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define <4 x i32> @testVINSWVRX(<4 x i32> %a, i32 %b, <4 x i32> %c) {
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; CHECK-LABEL: testVINSWVRX:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vinswvrx v2, r5, v3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i64 %b, <4 x i32> %c)
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i32 %b, <4 x i32> %c)
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ret <4 x i32> %0
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}
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declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
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declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i32, <4 x i32>)
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define <4 x i32> @testVINSW(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: testVINSW:
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