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Add load + store folding srl and sra patterns.
llvm-svn: 24696
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@ -1062,17 +1062,27 @@ def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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let isTwoAddress = 0 in {
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def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
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"shr{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shr{b} {%cl, $dst|$dst, %CL}",
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[(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>;
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def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
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"shr{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
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"shr{w} {%cl, $dst|$dst, %CL}",
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[(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>, OpSize;
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def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
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"shr{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"shr{l} {%cl, $dst|$dst, %CL}",
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[(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>;
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def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
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"shr{b} {$src, $dst|$dst, $src}", []>;
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"shr{b} {$src, $dst|$dst, $src}",
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[(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
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"shr{w} {$src, $dst|$dst, $src}", []>, OpSize;
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"shr{w} {$src, $dst|$dst, $src}",
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[(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
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OpSize;
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def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
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"shr{l} {$src, $dst|$dst, $src}", []>;
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"shr{l} {$src, $dst|$dst, $src}",
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[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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}
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def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
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@ -1097,17 +1107,27 @@ def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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[(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>;
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let isTwoAddress = 0 in {
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def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
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"sar{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"sar{b} {%cl, $dst|$dst, %CL}",
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[(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>;
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def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
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"sar{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
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"sar{w} {%cl, $dst|$dst, %CL}",
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[(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>, OpSize;
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def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
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"sar{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
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"sar{l} {%cl, $dst|$dst, %CL}",
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[(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
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Imp<[CL],[]>;
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def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
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"sar{b} {$src, $dst|$dst, $src}", []>;
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"sar{b} {$src, $dst|$dst, $src}",
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[(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
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"sar{w} {$src, $dst|$dst, $src}", []>, OpSize;
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"sar{w} {$src, $dst|$dst, $src}",
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[(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
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OpSize;
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def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
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"sar{l} {$src, $dst|$dst, $src}", []>;
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"sar{l} {$src, $dst|$dst, $src}",
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[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
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}
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// Rotate instructions
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