diff --git a/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp b/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
index 51af2505095..4fca8bec742 100644
--- a/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
+++ b/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
@@ -81,7 +81,8 @@ recursivelyVisitUsers(GlobalValue &GV,
       continue;
     }
 
-    append_range(Stack, U->users());
+    for (User *UU : U->users())
+      Stack.push_back(UU);
   }
 }
 
diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
index e959c5f0f8d..2ce1ac51c01 100644
--- a/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6208,10 +6208,12 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
   SmallVector<SDValue, 26> Ops;
   if (BaseOpcode->Store || BaseOpcode->Atomic)
     Ops.push_back(VData); // vdata
-  if (UseNSA)
-    append_range(Ops, VAddrs);
-  else
+  if (UseNSA) {
+    for (const SDValue &Addr : VAddrs)
+      Ops.push_back(Addr);
+  } else {
     Ops.push_back(VAddr);
+  }
   Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
   if (BaseOpcode->Sampler)
     Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));
diff --git a/lib/Target/AMDGPU/SILowerI1Copies.cpp b/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 9570680ad9c..18ab7d7cd55 100644
--- a/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -177,8 +177,10 @@ public:
         }
       }
 
-      if (Divergent && PDT.dominates(&DefBlock, MBB))
-        append_range(Stack, MBB->successors());
+      if (Divergent && PDT.dominates(&DefBlock, MBB)) {
+        for (MachineBasicBlock *Succ : MBB->successors())
+          Stack.push_back(Succ);
+      }
     }
 
     while (!Stack.empty()) {
@@ -187,7 +189,8 @@ public:
         continue;
       ReachableOrdered.push_back(MBB);
 
-      append_range(Stack, MBB->successors());
+      for (MachineBasicBlock *Succ : MBB->successors())
+        Stack.push_back(Succ);
     }
 
     for (MachineBasicBlock *MBB : ReachableOrdered) {
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 397979b4ab1..f6f8597f3a6 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -3556,7 +3556,8 @@ static bool allUsersAreInFunction(const Value *V, const Function *F) {
   while (!Worklist.empty()) {
     auto *U = Worklist.pop_back_val();
     if (isa<ConstantExpr>(U)) {
-      append_range(Worklist, U->users());
+      for (auto *UU : U->users())
+        Worklist.push_back(UU);
       continue;
     }
 
@@ -19125,7 +19126,8 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
 
       SmallVector<Value *, 6> Ops;
       Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
-      append_range(Ops, Shuffles);
+      for (auto S : Shuffles)
+        Ops.push_back(S);
       Ops.push_back(Builder.getInt32(SI->getAlignment()));
       Builder.CreateCall(VstNFunc, Ops);
     } else {
@@ -19141,7 +19143,8 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
 
       SmallVector<Value *, 6> Ops;
       Ops.push_back(Builder.CreateBitCast(BaseAddr, EltPtrTy));
-      append_range(Ops, Shuffles);
+      for (auto S : Shuffles)
+        Ops.push_back(S);
       for (unsigned F = 0; F < Factor; F++) {
         Ops.push_back(Builder.getInt32(F));
         Builder.CreateCall(VstNFunc, Ops);
diff --git a/lib/Target/ARM/ARMLowOverheadLoops.cpp b/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 61a924078f2..2b53f57a7f0 100644
--- a/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -143,7 +143,8 @@ namespace {
       // Insert exit blocks.
       SmallVector<MachineBasicBlock*, 2> ExitBlocks;
       ML.getExitBlocks(ExitBlocks);
-      append_range(Order, ExitBlocks);
+      for (auto *MBB : ExitBlocks)
+        Order.push_back(MBB);
 
       // Then add the loop body.
       Search(ML.getHeader());
diff --git a/lib/Target/ARM/ARMParallelDSP.cpp b/lib/Target/ARM/ARMParallelDSP.cpp
index 9a7c1f541aa..9a3776fe64a 100644
--- a/lib/Target/ARM/ARMParallelDSP.cpp
+++ b/lib/Target/ARM/ARMParallelDSP.cpp
@@ -202,7 +202,8 @@ namespace {
   public:
     WidenedLoad(SmallVectorImpl<LoadInst*> &Lds, LoadInst *Wide)
       : NewLd(Wide) {
-      append_range(Loads, Lds);
+      for (auto *I : Lds)
+        Loads.push_back(I);
     }
     LoadInst *getLoad() {
       return NewLd;
diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 29b75814da6..cf5ea5d53af 100644
--- a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -315,7 +315,8 @@ HexagonTargetLowering::getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
                               const SDLoc &dl, SelectionDAG &DAG) const {
   SmallVector<SDValue,4> IntOps;
   IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
-  append_range(IntOps, Ops);
+  for (const SDValue &Op : Ops)
+    IntOps.push_back(Op);
   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
 }
 
diff --git a/lib/Target/Hexagon/HexagonSplitDouble.cpp b/lib/Target/Hexagon/HexagonSplitDouble.cpp
index c8c66ebb69c..60c2feb766c 100644
--- a/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -574,9 +574,12 @@ void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
 
   LoopVector WorkQ;
 
-  append_range(WorkQ, *MLI);
-  for (unsigned i = 0; i < WorkQ.size(); ++i)
-    append_range(WorkQ, *WorkQ[i]);
+  for (auto I : *MLI)
+    WorkQ.push_back(I);
+  for (unsigned i = 0; i < WorkQ.size(); ++i) {
+    for (auto I : *WorkQ[i])
+      WorkQ.push_back(I);
+  }
 
   USet Rs;
   for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {
diff --git a/lib/Target/Hexagon/RDFDeadCode.cpp b/lib/Target/Hexagon/RDFDeadCode.cpp
index 894bdf38fe1..5a98debd3c0 100644
--- a/lib/Target/Hexagon/RDFDeadCode.cpp
+++ b/lib/Target/Hexagon/RDFDeadCode.cpp
@@ -195,7 +195,8 @@ bool DeadCodeElimination::erase(const SetVector<NodeId> &Nodes) {
     // If it's a code node, add all ref nodes from it.
     uint16_t Kind = BA.Addr->getKind();
     if (Kind == NodeAttrs::Stmt || Kind == NodeAttrs::Phi) {
-      append_range(DRNs, NodeAddr<CodeNode*>(BA).Addr->members(DFG));
+      for (auto N : NodeAddr<CodeNode*>(BA).Addr->members(DFG))
+        DRNs.push_back(N);
       DINs.push_back(DFG.addr<InstrNode*>(I));
     } else {
       llvm_unreachable("Unexpected code node");
diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp
index b9518d6d706..77ea232b066 100644
--- a/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ b/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -148,7 +148,9 @@ queue_preds:
       return false;
     }
 
-    append_range(Preds, MBB->predecessors());
+    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
+         PIE = MBB->pred_end(); PI != PIE; ++PI)
+      Preds.push_back(*PI);
   }
 
   do {
diff --git a/lib/Target/X86/X86PartialReduction.cpp b/lib/Target/X86/X86PartialReduction.cpp
index babd923e749..8784a3df177 100644
--- a/lib/Target/X86/X86PartialReduction.cpp
+++ b/lib/Target/X86/X86PartialReduction.cpp
@@ -392,7 +392,8 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
         break;
 
       // Push incoming values to the worklist.
-      append_range(Worklist, PN->incoming_values());
+      for (Value *InV : PN->incoming_values())
+        Worklist.push_back(InV);
 
       continue;
     }
@@ -401,7 +402,8 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
       if (BO->getOpcode() == Instruction::Add) {
         // Simple case. Single use, just push its operands to the worklist.
         if (BO->hasNUses(BO == Root ? 2 : 1)) {
-          append_range(Worklist, BO->operands());
+          for (Value *Op : BO->operands())
+            Worklist.push_back(Op);
           continue;
         }
 
@@ -424,7 +426,8 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
             continue;
 
           // The phi forms a loop with this Add, push its operands.
-          append_range(Worklist, BO->operands());
+          for (Value *Op : BO->operands())
+            Worklist.push_back(Op);
         }
       }
     }
diff --git a/lib/Target/X86/X86WinEHState.cpp b/lib/Target/X86/X86WinEHState.cpp
index 7db1504b8ac..8d8bd5e6b32 100644
--- a/lib/Target/X86/X86WinEHState.cpp
+++ b/lib/Target/X86/X86WinEHState.cpp
@@ -704,7 +704,8 @@ void WinEHStatePass::addStateStores(Function &F, WinEHFuncInfo &FuncInfo) {
     // enqueue it's successors to see if we can infer their states.
     InitialStates.insert({BB, PredState});
     FinalStates.insert({BB, PredState});
-    append_range(Worklist, successors(BB));
+    for (BasicBlock *SuccBB : successors(BB))
+      Worklist.push_back(SuccBB);
   }
 
   // Try to hoist stores from successors.