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[SelectionDAG] Use Align/MaybeAlign in calls to getLoad/getStore/getExtLoad/getTruncStore.

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The versions that take 'unsigned' will be removed in the future.

I tried to use getOriginalAlign instead of getAlign in some
places. getAlign factors in the minimum alignment implied by
the offset in the pointer info. Since we're also passing the
pointer info we can use the original alignment.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D87592
This commit is contained in:
Craig Topper 2020-09-14 13:54:50 -07:00
parent 1808eaba55
commit ad2bea0363
24 changed files with 186 additions and 208 deletions
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66
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -7048,7 +7048,7 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
SDValue NewStore = SDValue NewStore =
DAG.getStore(Chain, DL, SourceValue, FirstStore->getBasePtr(), DAG.getStore(Chain, DL, SourceValue, FirstStore->getBasePtr(),
FirstStore->getPointerInfo(), FirstStore->getAlignment()); FirstStore->getPointerInfo(), FirstStore->getAlign());
// Rely on other DAG combine rules to remove the other individual stores. // Rely on other DAG combine rules to remove the other individual stores.
DAG.ReplaceAllUsesWith(N, NewStore.getNode()); DAG.ReplaceAllUsesWith(N, NewStore.getNode());
@ -7231,10 +7231,10 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
if (!Allowed || !Fast) if (!Allowed || !Fast)
return SDValue(); return SDValue();
SDValue NewLoad = DAG.getExtLoad(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, SDValue NewLoad =
SDLoc(N), VT, Chain, FirstLoad->getBasePtr(), DAG.getExtLoad(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, SDLoc(N), VT,
FirstLoad->getPointerInfo(), MemVT, Chain, FirstLoad->getBasePtr(),
FirstLoad->getAlignment()); FirstLoad->getPointerInfo(), MemVT, FirstLoad->getAlign());
// Transfer chain users from old loads to the new load. // Transfer chain users from old loads to the new load.
for (LoadSDNode *L : Loads) for (LoadSDNode *L : Loads)
@ -9789,7 +9789,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
SDValue BasePtr = LN0->getBasePtr(); SDValue BasePtr = LN0->getBasePtr();
for (unsigned Idx = 0; Idx < NumSplits; Idx++) { for (unsigned Idx = 0; Idx < NumSplits; Idx++) {
const unsigned Offset = Idx * Stride; const unsigned Offset = Idx * Stride;
const unsigned Align = MinAlign(LN0->getAlignment(), Offset); const Align Align = commonAlignment(LN0->getAlign(), Offset);
SDValue SplitLoad = DAG.getExtLoad( SDValue SplitLoad = DAG.getExtLoad(
ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(), BasePtr, ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(), BasePtr,
@ -11015,7 +11015,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
ShAmt = AdjustBigEndianShift(ShAmt); ShAmt = AdjustBigEndianShift(ShAmt);
uint64_t PtrOff = ShAmt / 8; uint64_t PtrOff = ShAmt / 8;
unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); Align NewAlign = commonAlignment(LN0->getAlign(), PtrOff);
SDLoc DL(LN0); SDLoc DL(LN0);
// The original load itself didn't wrap, so an offset within it doesn't. // The original load itself didn't wrap, so an offset within it doesn't.
SDNodeFlags Flags; SDNodeFlags Flags;
@ -11735,7 +11735,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
*LN0->getMemOperand())) { *LN0->getMemOperand())) {
SDValue Load = SDValue Load =
DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
LN0->getPointerInfo(), LN0->getAlignment(), LN0->getPointerInfo(), LN0->getAlign(),
LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
return Load; return Load;
@ -15712,8 +15712,6 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
// Figure out the offset for the store and the alignment of the access. // Figure out the offset for the store and the alignment of the access.
unsigned StOffset; unsigned StOffset;
unsigned NewAlign = St->getAlignment();
if (DAG.getDataLayout().isLittleEndian()) if (DAG.getDataLayout().isLittleEndian())
StOffset = ByteShift; StOffset = ByteShift;
else else
@ -15723,7 +15721,6 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
if (StOffset) { if (StOffset) {
SDLoc DL(IVal); SDLoc DL(IVal);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(StOffset), DL); Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(StOffset), DL);
NewAlign = MinAlign(NewAlign, StOffset);
} }
// Truncate down to the new size. // Truncate down to the new size.
@ -15732,7 +15729,8 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
++OpsNarrowed; ++OpsNarrowed;
return DAG return DAG
.getStore(St->getChain(), SDLoc(St), IVal, Ptr, .getStore(St->getChain(), SDLoc(St), IVal, Ptr,
St->getPointerInfo().getWithOffset(StOffset), NewAlign); St->getPointerInfo().getWithOffset(StOffset),
St->getOriginalAlign());
} }
/// Look for sequence of load / op / store where op is one of 'or', 'xor', and /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
@ -16145,9 +16143,9 @@ bool DAGCombiner::mergeStoresOfConstantsOrVecElts(
// make sure we use trunc store if it's necessary to be legal. // make sure we use trunc store if it's necessary to be legal.
SDValue NewStore; SDValue NewStore;
if (!UseTrunc) { if (!UseTrunc) {
NewStore = DAG.getStore(NewChain, DL, StoredVal, FirstInChain->getBasePtr(), NewStore =
FirstInChain->getPointerInfo(), DAG.getStore(NewChain, DL, StoredVal, FirstInChain->getBasePtr(),
FirstInChain->getAlignment()); FirstInChain->getPointerInfo(), FirstInChain->getAlign());
} else { // Must be realized as a trunc store } else { // Must be realized as a trunc store
EVT LegalizedStoredValTy = EVT LegalizedStoredValTy =
TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType()); TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
@ -16159,8 +16157,7 @@ bool DAGCombiner::mergeStoresOfConstantsOrVecElts(
NewStore = DAG.getTruncStore( NewStore = DAG.getTruncStore(
NewChain, DL, ExtendedStoreVal, FirstInChain->getBasePtr(), NewChain, DL, ExtendedStoreVal, FirstInChain->getBasePtr(),
FirstInChain->getPointerInfo(), StoredVal.getValueType() /*TVT*/, FirstInChain->getPointerInfo(), StoredVal.getValueType() /*TVT*/,
FirstInChain->getAlignment(), FirstInChain->getAlign(), FirstInChain->getMemOperand()->getFlags());
FirstInChain->getMemOperand()->getFlags());
} }
// Replace all merged stores with the new store. // Replace all merged stores with the new store.
@ -16691,7 +16688,7 @@ bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
} }
LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
unsigned FirstStoreAS = FirstInChain->getAddressSpace(); unsigned FirstStoreAS = FirstInChain->getAddressSpace();
unsigned FirstStoreAlign = FirstInChain->getAlignment(); Align FirstStoreAlign = FirstInChain->getAlign();
LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
// Scan the memory operations on the chain and find the first // Scan the memory operations on the chain and find the first
@ -16786,7 +16783,7 @@ bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
// the NumElem refers to array/index size. // the NumElem refers to array/index size.
unsigned NumElem = std::min(NumConsecutiveStores, LastConsecutiveLoad + 1); unsigned NumElem = std::min(NumConsecutiveStores, LastConsecutiveLoad + 1);
NumElem = std::min(LastLegalType, NumElem); NumElem = std::min(LastLegalType, NumElem);
unsigned FirstLoadAlign = FirstLoad->getAlignment(); Align FirstLoadAlign = FirstLoad->getAlign();
if (NumElem < 2) { if (NumElem < 2) {
// We know that candidate stores are in order and of correct // We know that candidate stores are in order and of correct
@ -16798,8 +16795,8 @@ bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
// can here. // can here.
unsigned NumSkip = 1; unsigned NumSkip = 1;
while ((NumSkip < LoadNodes.size()) && while ((NumSkip < LoadNodes.size()) &&
(LoadNodes[NumSkip].MemNode->getAlignment() <= FirstLoadAlign) && (LoadNodes[NumSkip].MemNode->getAlign() <= FirstLoadAlign) &&
(StoreNodes[NumSkip].MemNode->getAlignment() <= FirstStoreAlign)) (StoreNodes[NumSkip].MemNode->getAlign() <= FirstStoreAlign))
NumSkip++; NumSkip++;
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip); StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumSkip);
LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumSkip); LoadNodes.erase(LoadNodes.begin(), LoadNodes.begin() + NumSkip);
@ -16872,11 +16869,10 @@ bool DAGCombiner::tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
FirstLoad->getChain(), FirstLoad->getBasePtr(), FirstLoad->getChain(), FirstLoad->getBasePtr(),
FirstLoad->getPointerInfo(), JointMemOpVT, FirstLoad->getPointerInfo(), JointMemOpVT,
FirstLoadAlign, LdMMOFlags); FirstLoadAlign, LdMMOFlags);
NewStore = DAG.getTruncStore(NewStoreChain, StoreDL, NewLoad, NewStore = DAG.getTruncStore(
FirstInChain->getBasePtr(), NewStoreChain, StoreDL, NewLoad, FirstInChain->getBasePtr(),
FirstInChain->getPointerInfo(), JointMemOpVT, FirstInChain->getPointerInfo(), JointMemOpVT,
FirstInChain->getAlignment(), FirstInChain->getAlign(), FirstInChain->getMemOperand()->getFlags());
FirstInChain->getMemOperand()->getFlags());
} }
// Transfer chain users from old loads to the new load. // Transfer chain users from old loads to the new load.
@ -17078,17 +17074,15 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
if (DAG.getDataLayout().isBigEndian()) if (DAG.getDataLayout().isBigEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
unsigned Alignment = ST->getAlignment();
MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
AAMDNodes AAInfo = ST->getAAInfo(); AAMDNodes AAInfo = ST->getAAInfo();
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(), SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
ST->getAlignment(), MMOFlags, AAInfo); ST->getOriginalAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), DL); Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(4), DL);
Alignment = MinAlign(Alignment, 4U);
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr, SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4), ST->getPointerInfo().getWithOffset(4),
Alignment, MMOFlags, AAInfo); ST->getOriginalAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
St0, St1); St0, St1);
} }
@ -17421,7 +17415,6 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
return SDValue(); return SDValue();
// Start to split store. // Start to split store.
unsigned Alignment = ST->getAlignment();
MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
AAMDNodes AAInfo = ST->getAAInfo(); AAMDNodes AAInfo = ST->getAAInfo();
@ -17434,13 +17427,12 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
SDValue Ptr = ST->getBasePtr(); SDValue Ptr = ST->getBasePtr();
// Lower value store. // Lower value store.
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(), SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
ST->getAlignment(), MMOFlags, AAInfo); ST->getOriginalAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(HalfValBitSize / 8), DL); Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(HalfValBitSize / 8), DL);
// Higher value store. // Higher value store.
SDValue St1 = SDValue St1 = DAG.getStore(
DAG.getStore(St0, DL, Hi, Ptr, St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8),
ST->getPointerInfo().getWithOffset(HalfValBitSize / 8), ST->getOriginalAlign(), MMOFlags, AAInfo);
Alignment / 2, MMOFlags, AAInfo);
return St1; return St1;
} }
@ -21229,7 +21221,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
// It is safe to replace the two loads if they have different alignments, // It is safe to replace the two loads if they have different alignments,
// but the new load must be the minimum (most restrictive) alignment of the // but the new load must be the minimum (most restrictive) alignment of the
// inputs. // inputs.
unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment()); Align Alignment = std::min(LLD->getAlign(), RLD->getAlign());
MachineMemOperand::Flags MMOFlags = LLD->getMemOperand()->getFlags(); MachineMemOperand::Flags MMOFlags = LLD->getMemOperand()->getFlags();
if (!RLD->isInvariant()) if (!RLD->isInvariant())
MMOFlags &= ~MachineMemOperand::MOInvariant; MMOFlags &= ~MachineMemOperand::MOInvariant;

6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1772,9 +1772,9 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
EVT DestVT, const SDLoc &dl, EVT DestVT, const SDLoc &dl,
SDValue Chain) { SDValue Chain) {
// Create the stack frame object. // Create the stack frame object.
unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment( Align SrcAlign = DAG.getDataLayout().getPrefTypeAlign(
SrcOp.getValueType().getTypeForEVT(*DAG.getContext())); SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); SDValue FIPtr = DAG.CreateStackTemporary(SlotVT.getStoreSize(), SrcAlign);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
int SPFI = StackPtrFI->getIndex(); int SPFI = StackPtrFI->getIndex();
@ -1785,7 +1785,7 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
unsigned SlotSize = SlotVT.getSizeInBits(); unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits(); unsigned DestSize = DestVT.getSizeInBits();
Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType); Align DestAlign = DAG.getDataLayout().getPrefTypeAlign(DestType);
// Emit a store to the stack slot. Use a truncstore if the input value is // Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT. // later than DestVT.

27
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -6103,7 +6103,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
Store = DAG.getStore( Store = DAG.getStore(
Chain, dl, Value, Chain, dl, Value,
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl), DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
DstPtrInfo.getWithOffset(DstOff), Alignment.value(), MMOFlags); DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags);
OutChains.push_back(Store); OutChains.push_back(Store);
} }
} }
@ -6127,13 +6127,13 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
ISD::EXTLOAD, dl, NVT, Chain, ISD::EXTLOAD, dl, NVT, Chain,
DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl), DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl),
SrcPtrInfo.getWithOffset(SrcOff), VT, SrcPtrInfo.getWithOffset(SrcOff), VT,
commonAlignment(*SrcAlign, SrcOff).value(), SrcMMOFlags); commonAlignment(*SrcAlign, SrcOff), SrcMMOFlags);
OutLoadChains.push_back(Value.getValue(1)); OutLoadChains.push_back(Value.getValue(1));
Store = DAG.getTruncStore( Store = DAG.getTruncStore(
Chain, dl, Value, Chain, dl, Value,
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl), DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
DstPtrInfo.getWithOffset(DstOff), VT, Alignment.value(), MMOFlags); DstPtrInfo.getWithOffset(DstOff), VT, Alignment, MMOFlags);
OutStoreChains.push_back(Store); OutStoreChains.push_back(Store);
} }
SrcOff += VTSize; SrcOff += VTSize;
@ -6253,10 +6253,10 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
if (isDereferenceable) if (isDereferenceable)
SrcMMOFlags |= MachineMemOperand::MODereferenceable; SrcMMOFlags |= MachineMemOperand::MODereferenceable;
Value = DAG.getLoad( Value =
VT, dl, Chain, DAG.getLoad(VT, dl, Chain,
DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl), DAG.getMemBasePlusOffset(Src, TypeSize::Fixed(SrcOff), dl),
SrcPtrInfo.getWithOffset(SrcOff), SrcAlign->value(), SrcMMOFlags); SrcPtrInfo.getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags);
LoadValues.push_back(Value); LoadValues.push_back(Value);
LoadChains.push_back(Value.getValue(1)); LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize; SrcOff += VTSize;
@ -6268,10 +6268,10 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
unsigned VTSize = VT.getSizeInBits() / 8; unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Store; SDValue Store;
Store = DAG.getStore( Store =
Chain, dl, LoadValues[i], DAG.getStore(Chain, dl, LoadValues[i],
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl), DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
DstPtrInfo.getWithOffset(DstOff), Alignment.value(), MMOFlags); DstPtrInfo.getWithOffset(DstOff), Alignment, MMOFlags);
OutChains.push_back(Store); OutChains.push_back(Store);
DstOff += VTSize; DstOff += VTSize;
} }
@ -6371,7 +6371,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
SDValue Store = DAG.getStore( SDValue Store = DAG.getStore(
Chain, dl, Value, Chain, dl, Value,
DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl), DAG.getMemBasePlusOffset(Dst, TypeSize::Fixed(DstOff), dl),
DstPtrInfo.getWithOffset(DstOff), Alignment.value(), DstPtrInfo.getWithOffset(DstOff), Alignment,
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone); isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone);
OutChains.push_back(Store); OutChains.push_back(Store);
DstOff += VT.getSizeInBits() / 8; DstOff += VT.getSizeInBits() / 8;
@ -7036,8 +7036,7 @@ SDValue SelectionDAG::getIndexedLoad(SDValue OrigLoad, const SDLoc &dl,
~(MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable); ~(MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable);
return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl, return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
LD->getChain(), Base, Offset, LD->getPointerInfo(), LD->getChain(), Base, Offset, LD->getPointerInfo(),
LD->getMemoryVT(), LD->getAlignment(), MMOFlags, LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
LD->getAAInfo());
} }
SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,

17
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -2539,7 +2539,7 @@ void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
SDLoc dl = getCurSDLoc(); SDLoc dl = getCurSDLoc();
SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy); SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
const Module &M = *ParentBB->getParent()->getFunction().getParent(); const Module &M = *ParentBB->getParent()->getFunction().getParent();
unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext())); Align Align = DL->getPrefTypeAlign(Type::getInt8PtrTy(M.getContext()));
// Generate code to load the content of the guard slot. // Generate code to load the content of the guard slot.
SDValue GuardVal = DAG.getLoad( SDValue GuardVal = DAG.getLoad(
@ -6380,7 +6380,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
} else { } else {
EVT PtrTy = TLI.getValueType(DAG.getDataLayout(), I.getType()); EVT PtrTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
const Value *Global = TLI.getSDagStackGuard(M); const Value *Global = TLI.getSDagStackGuard(M);
unsigned Align = DL->getPrefTypeAlignment(Global->getType()); Align Align = DL->getPrefTypeAlign(Global->getType());
Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global), Res = DAG.getLoad(PtrTy, sdl, Chain, getValue(Global),
MachinePointerInfo(Global, 0), Align, MachinePointerInfo(Global, 0), Align,
MachineMemOperand::MOVolatile); MachineMemOperand::MOVolatile);
@ -6411,9 +6411,10 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
SDValue FIN = DAG.getFrameIndex(FI, PtrTy); SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
// Store the stack protector onto the stack. // Store the stack protector onto the stack.
Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack( Res = DAG.getStore(
DAG.getMachineFunction(), FI), Chain, sdl, Src, FIN,
/* Alignment = */ 0, MachineMemOperand::MOVolatile); MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
MaybeAlign(), MachineMemOperand::MOVolatile);
setValue(&I, Res); setValue(&I, Res);
DAG.setRoot(Res); DAG.setRoot(Res);
return; return;
@ -7245,9 +7246,9 @@ static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
} }
SDValue Ptr = Builder.getValue(PtrVal); SDValue Ptr = Builder.getValue(PtrVal);
SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, SDValue LoadVal =
Ptr, MachinePointerInfo(PtrVal), Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr,
/* Alignment = */ 1); MachinePointerInfo(PtrVal), Align(1));
if (!ConstantMemory) if (!ConstantMemory)
Builder.PendingLoads.push_back(LoadVal.getValue(1)); Builder.PendingLoads.push_back(LoadVal.getValue(1));

41
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -3601,10 +3601,10 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (bestOffset != 0) if (bestOffset != 0)
Ptr = Ptr =
DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(bestOffset), dl); DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(bestOffset), dl);
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); SDValue NewLoad =
SDValue NewLoad = DAG.getLoad( DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
newVT, dl, Lod->getChain(), Ptr, Lod->getPointerInfo().getWithOffset(bestOffset),
Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign); Lod->getOriginalAlign());
return DAG.getSetCC(dl, VT, return DAG.getSetCC(dl, VT,
DAG.getNode(ISD::AND, dl, newVT, NewLoad, DAG.getNode(ISD::AND, dl, newVT, NewLoad,
DAG.getConstant(bestMask.trunc(bestWidth), DAG.getConstant(bestMask.trunc(bestWidth),
@ -6817,7 +6817,7 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
// the codegen worse. // the codegen worse.
SDValue Load = SDValue Load =
DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR,
LD->getPointerInfo(), SrcIntVT, LD->getAlignment(), LD->getPointerInfo(), SrcIntVT, LD->getOriginalAlign(),
LD->getMemOperand()->getFlags(), LD->getAAInfo()); LD->getMemOperand()->getFlags(), LD->getAAInfo());
SmallVector<SDValue, 8> Vals; SmallVector<SDValue, 8> Vals;
@ -6854,7 +6854,7 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
SDValue ScalarLoad = SDValue ScalarLoad =
DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR, DAG.getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
LD->getPointerInfo().getWithOffset(Idx * Stride), LD->getPointerInfo().getWithOffset(Idx * Stride),
SrcEltVT, MinAlign(LD->getAlignment(), Idx * Stride), SrcEltVT, LD->getOriginalAlign(),
LD->getMemOperand()->getFlags(), LD->getAAInfo()); LD->getMemOperand()->getFlags(), LD->getAAInfo());
BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, TypeSize::Fixed(Stride)); BasePTR = DAG.getObjectPtrOffset(SL, BasePTR, TypeSize::Fixed(Stride));
@ -6917,7 +6917,7 @@ SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
} }
return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(), return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
ST->getAlignment(), ST->getMemOperand()->getFlags(), ST->getOriginalAlign(), ST->getMemOperand()->getFlags(),
ST->getAAInfo()); ST->getAAInfo());
} }
@ -6937,8 +6937,8 @@ SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
// This scalar TruncStore may be illegal, but we legalize it later. // This scalar TruncStore may be illegal, but we legalize it later.
SDValue Store = DAG.getTruncStore( SDValue Store = DAG.getTruncStore(
Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride), Chain, SL, Elt, Ptr, ST->getPointerInfo().getWithOffset(Idx * Stride),
MemSclVT, MinAlign(ST->getAlignment(), Idx * Stride), MemSclVT, ST->getOriginalAlign(), ST->getMemOperand()->getFlags(),
ST->getMemOperand()->getFlags(), ST->getAAInfo()); ST->getAAInfo());
Stores.push_back(Store); Stores.push_back(Store);
} }
@ -7003,7 +7003,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
// Load one integer register's worth from the original location. // Load one integer register's worth from the original location.
SDValue Load = DAG.getLoad( SDValue Load = DAG.getLoad(
RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset),
MinAlign(LD->getAlignment(), Offset), LD->getMemOperand()->getFlags(), LD->getOriginalAlign(), LD->getMemOperand()->getFlags(),
LD->getAAInfo()); LD->getAAInfo());
// Follow the load with a store to the stack slot. Remember the store. // Follow the load with a store to the stack slot. Remember the store.
Stores.push_back(DAG.getStore( Stores.push_back(DAG.getStore(
@ -7022,8 +7022,8 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
SDValue Load = SDValue Load =
DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
LD->getPointerInfo().getWithOffset(Offset), MemVT, LD->getPointerInfo().getWithOffset(Offset), MemVT,
MinAlign(LD->getAlignment(), Offset), LD->getOriginalAlign(), LD->getMemOperand()->getFlags(),
LD->getMemOperand()->getFlags(), LD->getAAInfo()); LD->getAAInfo());
// Follow the load with a store to the stack slot. Remember the store. // Follow the load with a store to the stack slot. Remember the store.
// On big-endian machines this requires a truncating store to ensure // On big-endian machines this requires a truncating store to ensure
// that the bits end up in the right place. // that the bits end up in the right place.
@ -7053,7 +7053,7 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
NumBits >>= 1; NumBits >>= 1;
unsigned Alignment = LD->getAlignment(); Align Alignment = LD->getOriginalAlign();
unsigned IncrementSize = NumBits / 8; unsigned IncrementSize = NumBits / 8;
ISD::LoadExtType HiExtType = LD->getExtensionType(); ISD::LoadExtType HiExtType = LD->getExtensionType();
@ -7071,8 +7071,8 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
NewLoadedVT, MinAlign(Alignment, IncrementSize), NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
LD->getMemOperand()->getFlags(), LD->getAAInfo()); LD->getAAInfo());
} else { } else {
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(), NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
@ -7081,8 +7081,8 @@ TargetLowering::expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const {
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
NewLoadedVT, MinAlign(Alignment, IncrementSize), NewLoadedVT, Alignment, LD->getMemOperand()->getFlags(),
LD->getMemOperand()->getFlags(), LD->getAAInfo()); LD->getAAInfo());
} }
// aggregate the two parts // aggregate the two parts
@ -7106,7 +7106,7 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
SDValue Ptr = ST->getBasePtr(); SDValue Ptr = ST->getBasePtr();
SDValue Val = ST->getValue(); SDValue Val = ST->getValue();
EVT VT = Val.getValueType(); EVT VT = Val.getValueType();
int Alignment = ST->getAlignment(); Align Alignment = ST->getOriginalAlign();
auto &MF = DAG.getMachineFunction(); auto &MF = DAG.getMachineFunction();
EVT StoreMemVT = ST->getMemoryVT(); EVT StoreMemVT = ST->getMemoryVT();
@ -7163,7 +7163,7 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
// Store it to the final location. Remember the store. // Store it to the final location. Remember the store.
Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
ST->getPointerInfo().getWithOffset(Offset), ST->getPointerInfo().getWithOffset(Offset),
MinAlign(ST->getAlignment(), Offset), ST->getOriginalAlign(),
ST->getMemOperand()->getFlags())); ST->getMemOperand()->getFlags()));
// Increment the pointers. // Increment the pointers.
Offset += RegBytes; Offset += RegBytes;
@ -7185,7 +7185,7 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
Stores.push_back( Stores.push_back(
DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
ST->getPointerInfo().getWithOffset(Offset), LoadMemVT, ST->getPointerInfo().getWithOffset(Offset), LoadMemVT,
MinAlign(ST->getAlignment(), Offset), ST->getOriginalAlign(),
ST->getMemOperand()->getFlags(), ST->getAAInfo())); ST->getMemOperand()->getFlags(), ST->getAAInfo()));
// The order of the stores doesn't matter - say it with a TokenFactor. // The order of the stores doesn't matter - say it with a TokenFactor.
SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
@ -7213,7 +7213,6 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
ST->getMemOperand()->getFlags()); ST->getMemOperand()->getFlags());
Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize)); Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
Alignment = MinAlign(Alignment, IncrementSize);
Store2 = DAG.getTruncStore( Store2 = DAG.getTruncStore(
Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr, Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment, ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT, Alignment,

24
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -5273,7 +5273,7 @@ AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
SDValue FuncTLVGet = DAG.getLoad( SDValue FuncTLVGet = DAG.getLoad(
PtrMemVT, DL, Chain, DescAddr, PtrMemVT, DL, Chain, DescAddr,
MachinePointerInfo::getGOT(DAG.getMachineFunction()), MachinePointerInfo::getGOT(DAG.getMachineFunction()),
/* Alignment = */ PtrMemVT.getSizeInBits() / 8, Align(PtrMemVT.getSizeInBits() / 8),
MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable); MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable);
Chain = FuncTLVGet.getValue(1); Chain = FuncTLVGet.getValue(1);
@ -6302,8 +6302,8 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
// void *__stack at offset 0 // void *__stack at offset 0
SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT); SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, MemOps.push_back(
MachinePointerInfo(SV), /* Alignment = */ 8)); DAG.getStore(Chain, DL, Stack, VAList, MachinePointerInfo(SV), Align(8)));
// void *__gr_top at offset 8 // void *__gr_top at offset 8
int GPRSize = FuncInfo->getVarArgsGPRSize(); int GPRSize = FuncInfo->getVarArgsGPRSize();
@ -6318,8 +6318,7 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
DAG.getConstant(GPRSize, DL, PtrVT)); DAG.getConstant(GPRSize, DL, PtrVT));
MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
MachinePointerInfo(SV, 8), MachinePointerInfo(SV, 8), Align(8)));
/* Alignment = */ 8));
} }
// void *__vr_top at offset 16 // void *__vr_top at offset 16
@ -6334,23 +6333,22 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
DAG.getConstant(FPRSize, DL, PtrVT)); DAG.getConstant(FPRSize, DL, PtrVT));
MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
MachinePointerInfo(SV, 16), MachinePointerInfo(SV, 16), Align(8)));
/* Alignment = */ 8));
} }
// int __gr_offs at offset 24 // int __gr_offs at offset 24
SDValue GROffsAddr = SDValue GROffsAddr =
DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT)); DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
MemOps.push_back(DAG.getStore( MemOps.push_back(
Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32), GROffsAddr, DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32),
MachinePointerInfo(SV, 24), /* Alignment = */ 4)); GROffsAddr, MachinePointerInfo(SV, 24), Align(4)));
// int __vr_offs at offset 28 // int __vr_offs at offset 28
SDValue VROffsAddr = SDValue VROffsAddr =
DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT)); DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
MemOps.push_back(DAG.getStore( MemOps.push_back(
Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32), VROffsAddr, DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32),
MachinePointerInfo(SV, 28), /* Alignment = */ 4)); VROffsAddr, MachinePointerInfo(SV, 28), Align(4)));
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
} }

6
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
View File

@ -4164,9 +4164,9 @@ SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset); auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32); SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4, return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, Align(4),
MachineMemOperand::MODereferenceable | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant); MachineMemOperand::MOInvariant);
} }
SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG, SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
@ -4178,7 +4178,7 @@ SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset); MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32); SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4, SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, Align(4),
MachineMemOperand::MODereferenceable); MachineMemOperand::MODereferenceable);
return Store; return Store;
} }

10
lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -1665,9 +1665,9 @@ SDValue SITargetLowering::lowerKernargMemParameter(
// TODO: If we passed in the base kernel offset we could have a better // TODO: If we passed in the base kernel offset we could have a better
// alignment than 4, but we don't really need it. // alignment than 4, but we don't really need it.
SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset); SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, 4, SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4),
MachineMemOperand::MODereferenceable | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant); MachineMemOperand::MOInvariant);
SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32); SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt); SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
@ -3074,8 +3074,8 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
MemOpChains.push_back(Cpy); MemOpChains.push_back(Cpy);
} else { } else {
SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, SDValue Store =
Alignment ? Alignment->value() : 0); DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, Alignment);
MemOpChains.push_back(Store); MemOpChains.push_back(Store);
} }
} }
@ -5231,7 +5231,7 @@ SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
// be available and how do we get it? // be available and how do we get it?
MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS); MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo, return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
MinAlign(64, StructOffset), commonAlignment(Align(64), StructOffset),
MachineMemOperand::MODereferenceable | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant); MachineMemOperand::MOInvariant);
} }

11
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -2517,9 +2517,9 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY)); DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
Callee = DAG.getLoad( Callee = DAG.getLoad(
PtrVt, dl, DAG.getEntryNode(), Callee, PtrVt, dl, DAG.getEntryNode(), Callee,
MachinePointerInfo::getGOT(DAG.getMachineFunction()), MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
/* Alignment = */ 0, MachineMemOperand::MODereferenceable | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant); MachineMemOperand::MOInvariant);
} else if (Subtarget->isTargetCOFF()) { } else if (Subtarget->isTargetCOFF()) {
assert(Subtarget->isTargetWindows() && assert(Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target"); "Windows is the only supported COFF target");
@ -3328,8 +3328,7 @@ ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
SDValue Chain = DAG.getEntryNode(); SDValue Chain = DAG.getEntryNode();
SDValue FuncTLVGet = DAG.getLoad( SDValue FuncTLVGet = DAG.getLoad(
MVT::i32, DL, Chain, DescAddr, MVT::i32, DL, Chain, DescAddr,
MachinePointerInfo::getGOT(DAG.getMachineFunction()), MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
/* Alignment = */ 4,
MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable | MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant); MachineMemOperand::MOInvariant);
Chain = FuncTLVGet.getValue(1); Chain = FuncTLVGet.getValue(1);
@ -15336,7 +15335,7 @@ static SDValue PerformSplittingToWideningLoad(SDNode *N, SelectionDAG &DAG) {
SDValue NewLoad = SDValue NewLoad =
DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset,
LD->getPointerInfo().getWithOffset(NewOffset), NewFromVT, LD->getPointerInfo().getWithOffset(NewOffset), NewFromVT,
Alignment.value(), MMOFlags, AAInfo); Alignment, MMOFlags, AAInfo);
Loads.push_back(NewLoad); Loads.push_back(NewLoad);
Chains.push_back(SDValue(NewLoad.getNode(), 1)); Chains.push_back(SDValue(NewLoad.getNode(), 1));
} }

8
lib/Target/AVR/AVRISelLowering.cpp
View File

@ -676,7 +676,7 @@ SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL)); SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
MachinePointerInfo(SV), 0); MachinePointerInfo(SV));
} }
SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
@ -1096,8 +1096,7 @@ SDValue AVRTargetLowering::LowerFormalArguments(
// from this parameter. // from this parameter.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL)); SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN, InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
MachinePointerInfo::getFixedStack(MF, FI), MachinePointerInfo::getFixedStack(MF, FI)));
0));
} }
} }
@ -1230,8 +1229,7 @@ SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Chain = Chain =
DAG.getStore(Chain, DL, Arg, PtrOff, DAG.getStore(Chain, DL, Arg, PtrOff,
MachinePointerInfo::getStack(MF, VA.getLocMemOffset()), MachinePointerInfo::getStack(MF, VA.getLocMemOffset()));
0);
} }
} }

4
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -231,10 +231,10 @@ SDNode *HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(MachineSDNode *LoadN,
if (Size >= 4) if (Size >= 4)
TS = CurDAG->getStore(SDValue(LoadN, 2), dl, SDValue(LoadN, 0), Loc, PI, TS = CurDAG->getStore(SDValue(LoadN, 2), dl, SDValue(LoadN, 0), Loc, PI,
Size); Align(Size));
else else
TS = CurDAG->getTruncStore(SDValue(LoadN, 2), dl, SDValue(LoadN, 0), Loc, TS = CurDAG->getTruncStore(SDValue(LoadN, 2), dl, SDValue(LoadN, 0), Loc,
PI, MVT::getIntegerVT(Size * 8), Size); PI, MVT::getIntegerVT(Size * 8), Align(Size));
SDNode *StoreN; SDNode *StoreN;
{ {

8
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3025,8 +3025,8 @@ SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(),
/* Alignment = */ 0, MachineMemOperand::MOVolatile); MachineMemOperand::MOVolatile);
} }
void MipsTargetLowering:: void MipsTargetLowering::
@ -4404,7 +4404,7 @@ void MipsTargetLowering::passByValArg(
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
DAG.getConstant(OffsetInBytes, DL, PtrTy)); DAG.getConstant(OffsetInBytes, DL, PtrTy));
SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
MachinePointerInfo(), Alignment.value()); MachinePointerInfo(), Alignment);
MemOpChains.push_back(LoadVal.getValue(1)); MemOpChains.push_back(LoadVal.getValue(1));
unsigned ArgReg = ArgRegs[FirstReg + I]; unsigned ArgReg = ArgRegs[FirstReg + I];
RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
@ -4431,7 +4431,7 @@ void MipsTargetLowering::passByValArg(
PtrTy)); PtrTy));
SDValue LoadVal = DAG.getExtLoad( SDValue LoadVal = DAG.getExtLoad(
ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment.value()); MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
MemOpChains.push_back(LoadVal.getValue(1)); MemOpChains.push_back(LoadVal.getValue(1));
// Shift the loaded value. // Shift the loaded value.

4
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -2307,7 +2307,7 @@ static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
/* Alignment = */ 16); Align(16));
} }
SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
@ -2382,7 +2382,7 @@ static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
/* Alignment = */ 16); Align(16));
} }
SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,

4
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -2139,7 +2139,7 @@ SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
int FI = MFI.CreateStackObject(16, Align(8), false); int FI = MFI.CreateStackObject(16, Align(8), false);
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(), Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(),
/* Alignment = */ 8); Align(8));
Entry.Node = FIPtr; Entry.Node = FIPtr;
Entry.Ty = PointerType::getUnqual(ArgTy); Entry.Ty = PointerType::getUnqual(ArgTy);
@ -2198,7 +2198,7 @@ SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
// Load RetPtr to get the return value. // Load RetPtr to get the return value.
return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr, return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
MachinePointerInfo(), /* Alignment = */ 8); MachinePointerInfo(), Align(8));
} }
SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,

5
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
View File

@ -117,9 +117,8 @@ SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemset(
return Chain1; return Chain1;
SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
DAG.getConstant(1, DL, PtrVT)); DAG.getConstant(1, DL, PtrVT));
SDValue Chain2 = SDValue Chain2 = DAG.getStore(Chain, DL, Byte, Dst2,
DAG.getStore(Chain, DL, Byte, Dst2, DstPtrInfo.getWithOffset(1), DstPtrInfo.getWithOffset(1), Align(1));
/* Alignment = */ 1);
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
} }
} }

4
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
View File

@ -904,7 +904,7 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
DAG.getConstant(Offset, DL, PtrVT)); DAG.getConstant(Offset, DL, PtrVT));
Chains.push_back( Chains.push_back(
DAG.getStore(Chain, DL, Arg, Add, DAG.getStore(Chain, DL, Arg, Add,
MachinePointerInfo::getFixedStack(MF, FI, Offset), 0)); MachinePointerInfo::getFixedStack(MF, FI, Offset)));
} }
if (!Chains.empty()) if (!Chains.empty())
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
@ -1331,7 +1331,7 @@ SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
SDValue ArgN = DAG.getCopyFromReg(DAG.getEntryNode(), DL, SDValue ArgN = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
MFI->getVarargBufferVreg(), PtrVT); MFI->getVarargBufferVreg(), PtrVT);
return DAG.getStore(Op.getOperand(0), DL, ArgN, Op.getOperand(1), return DAG.getStore(Op.getOperand(0), DL, ArgN, Op.getOperand(1),
MachinePointerInfo(SV), 0); MachinePointerInfo(SV));
} }
SDValue WebAssemblyTargetLowering::LowerIntrinsic(SDValue Op, SDValue WebAssemblyTargetLowering::LowerIntrinsic(SDValue Op,

58
lib/Target/X86/X86ISelLowering.cpp
View File

@ -19835,17 +19835,15 @@ static SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG,
// Load the 64-bit value into an XMM register. // Load the 64-bit value into an XMM register.
SDValue XR1 = SDValue XR1 =
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Op.getOperand(OpNo)); DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Op.getOperand(OpNo));
SDValue CLod0 = SDValue CLod0 = DAG.getLoad(
DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Align(16));
/* Alignment = */ 16);
SDValue Unpck1 = SDValue Unpck1 =
getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0); getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
SDValue CLod1 = SDValue CLod1 = DAG.getLoad(
DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Align(16));
/* Alignment = */ 16);
SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1); SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
SDValue Sub; SDValue Sub;
SDValue Chain; SDValue Chain;
@ -20211,17 +20209,17 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
// Make a 64-bit buffer, and use it to build an FILD. // Make a 64-bit buffer, and use it to build an FILD.
SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64, 8); SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64, 8);
int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
Align SlotAlign(8);
MachinePointerInfo MPI = MachinePointerInfo MPI =
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI); MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI);
if (SrcVT == MVT::i32) { if (SrcVT == MVT::i32) {
SDValue OffsetSlot = SDValue OffsetSlot =
DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), dl); DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), dl);
SDValue Store1 = SDValue Store1 = DAG.getStore(Chain, dl, Src, StackSlot, MPI, SlotAlign);
DAG.getStore(Chain, dl, Src, StackSlot, MPI, 8 /*Align*/);
SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32), SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
OffsetSlot, MPI.getWithOffset(4), 4); OffsetSlot, MPI.getWithOffset(4), SlotAlign);
std::pair<SDValue, SDValue> Tmp = std::pair<SDValue, SDValue> Tmp =
BuildFILD(DstVT, MVT::i64, dl, Store2, StackSlot, MPI, Align(8), DAG); BuildFILD(DstVT, MVT::i64, dl, Store2, StackSlot, MPI, SlotAlign, DAG);
if (IsStrict) if (IsStrict)
return DAG.getMergeValues({Tmp.first, Tmp.second}, dl); return DAG.getMergeValues({Tmp.first, Tmp.second}, dl);
@ -20237,7 +20235,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
ValueToStore = DAG.getBitcast(MVT::f64, ValueToStore); ValueToStore = DAG.getBitcast(MVT::f64, ValueToStore);
} }
SDValue Store = SDValue Store =
DAG.getStore(Chain, dl, ValueToStore, StackSlot, MPI, Align(8)); DAG.getStore(Chain, dl, ValueToStore, StackSlot, MPI, SlotAlign);
// For i64 source, we need to add the appropriate power of 2 if the input // For i64 source, we need to add the appropriate power of 2 if the input
// was negative. We must be careful to do the computation in x87 extended // was negative. We must be careful to do the computation in x87 extended
// precision, not in SSE. // precision, not in SSE.
@ -20245,7 +20243,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
SDValue Ops[] = { Store, StackSlot }; SDValue Ops[] = { Store, StackSlot };
SDValue Fild = SDValue Fild =
DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, MVT::i64, MPI, DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, MVT::i64, MPI,
Align(8), MachineMemOperand::MOLoad); SlotAlign, MachineMemOperand::MOLoad);
Chain = Fild.getValue(1); Chain = Fild.getValue(1);
@ -26298,9 +26296,8 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(2, dl, MVT::i64)); DAG.getConstant(2, dl, MVT::i64));
OutChains[1] = OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
DAG.getStore(Root, dl, FPtr, Addr, MachinePointerInfo(TrmpAddr, 2), MachinePointerInfo(TrmpAddr, 2), Align(2));
/* Alignment = */ 2);
// Load the 'nest' parameter value into R10. // Load the 'nest' parameter value into R10.
// R10 is specified in X86CallingConv.td // R10 is specified in X86CallingConv.td
@ -26312,9 +26309,8 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(12, dl, MVT::i64)); DAG.getConstant(12, dl, MVT::i64));
OutChains[3] = OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
DAG.getStore(Root, dl, Nest, Addr, MachinePointerInfo(TrmpAddr, 12), MachinePointerInfo(TrmpAddr, 12), Align(2));
/* Alignment = */ 2);
// Jump to the nested function. // Jump to the nested function.
OpCode = (JMP64r << 8) | REX_WB; // jmpq *... OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
@ -26394,22 +26390,20 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(1, dl, MVT::i32)); DAG.getConstant(1, dl, MVT::i32));
OutChains[1] = OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
DAG.getStore(Root, dl, Nest, Addr, MachinePointerInfo(TrmpAddr, 1), MachinePointerInfo(TrmpAddr, 1), Align(1));
/* Alignment = */ 1);
const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(5, dl, MVT::i32)); DAG.getConstant(5, dl, MVT::i32));
OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8), OutChains[2] =
Addr, MachinePointerInfo(TrmpAddr, 5), DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8), Addr,
/* Alignment = */ 1); MachinePointerInfo(TrmpAddr, 5), Align(1));
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(6, dl, MVT::i32)); DAG.getConstant(6, dl, MVT::i32));
OutChains[3] = OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
DAG.getStore(Root, dl, Disp, Addr, MachinePointerInfo(TrmpAddr, 6), MachinePointerInfo(TrmpAddr, 6), Align(1));
/* Alignment = */ 1);
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
} }
@ -27197,8 +27191,8 @@ SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) cons
MachinePointerInfo MPI = MachinePointerInfo MPI =
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI); MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
Entry.Node = StackPtr; Entry.Node = StackPtr;
InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, InChain =
MPI, /* Alignment = */ 16); DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MPI, Align(16));
Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
Entry.Ty = PointerType::get(ArgTy,0); Entry.Ty = PointerType::get(ArgTy,0);
Entry.IsSExt = false; Entry.IsSExt = false;
@ -29059,7 +29053,7 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG,
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI); MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
Chain = Chain =
DAG.getStore(Node->getChain(), dl, Node->getOperand(2), StackPtr, DAG.getStore(Node->getChain(), dl, Node->getOperand(2), StackPtr,
MPI, /*Align*/ 0, MachineMemOperand::MOStore); MPI, MaybeAlign(), MachineMemOperand::MOStore);
SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
SDValue LdOps[] = {Chain, StackPtr}; SDValue LdOps[] = {Chain, StackPtr};
SDValue Value = SDValue Value =

17
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -443,16 +443,15 @@ SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
} }
if (LD->getAlignment() == 2) { if (LD->getAlignment() == 2) {
SDValue Low = SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,
DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, LD->getPointerInfo(), MVT::i16, Align(2),
LD->getPointerInfo(), MVT::i16, LD->getMemOperand()->getFlags());
/* Alignment = */ 2, LD->getMemOperand()->getFlags());
SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
DAG.getConstant(2, DL, MVT::i32)); DAG.getConstant(2, DL, MVT::i32));
SDValue High = SDValue High =
DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr, DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr,
LD->getPointerInfo().getWithOffset(2), MVT::i16, LD->getPointerInfo().getWithOffset(2), MVT::i16,
/* Alignment = */ 2, LD->getMemOperand()->getFlags()); Align(2), LD->getMemOperand()->getFlags());
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
DAG.getConstant(16, DL, MVT::i32)); DAG.getConstant(16, DL, MVT::i32));
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
@ -502,14 +501,14 @@ SDValue XCoreTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
SDValue Low = Value; SDValue Low = Value;
SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
DAG.getConstant(16, dl, MVT::i32)); DAG.getConstant(16, dl, MVT::i32));
SDValue StoreLow = DAG.getTruncStore( SDValue StoreLow =
Chain, dl, Low, BasePtr, ST->getPointerInfo(), MVT::i16, DAG.getTruncStore(Chain, dl, Low, BasePtr, ST->getPointerInfo(),
/* Alignment = */ 2, ST->getMemOperand()->getFlags()); MVT::i16, Align(2), ST->getMemOperand()->getFlags());
SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
DAG.getConstant(2, dl, MVT::i32)); DAG.getConstant(2, dl, MVT::i32));
SDValue StoreHigh = DAG.getTruncStore( SDValue StoreHigh = DAG.getTruncStore(
Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2), Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2),
MVT::i16, /* Alignment = */ 2, ST->getMemOperand()->getFlags()); MVT::i16, Align(2), ST->getMemOperand()->getFlags());
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
} }

4
test/CodeGen/AArch64/sadd_sat_vec.ll
View File

@ -159,8 +159,8 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2]
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
@ -201,8 +201,8 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2]
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py

4
test/CodeGen/AArch64/ssub_sat_vec.ll
View File

@ -160,8 +160,8 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2]
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
@ -202,8 +202,8 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2]
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py

4
test/CodeGen/AArch64/uadd_sat_vec.ll
View File

@ -159,8 +159,8 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2]
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
@ -201,8 +201,8 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2]
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py

4
test/CodeGen/AArch64/usub_sat_vec.ll
View File

@ -160,8 +160,8 @@ define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #24 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2]
; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
@ -202,8 +202,8 @@ define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-NEXT: ushr v0.2s, v0.2s, #16 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2]
; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py

10
test/CodeGen/AMDGPU/private-element-size.ll
View File

@ -141,8 +141,8 @@ entry:
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}} ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
define amdgpu_kernel void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
@ -177,8 +177,8 @@ entry:
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:24{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:28{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}} ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
define amdgpu_kernel void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
@ -224,10 +224,10 @@ entry:
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:40{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:40{{$}}
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:44{{$}} ; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], 0 offset:44{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:8{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:12{{$}} ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:12{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:8{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen offset:4{{$}}
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}
define amdgpu_kernel void @private_elt_size_v2i64(<2 x i64> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_v2i64(<2 x i64> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()

46
test/CodeGen/PowerPC/aix-cc-abi.ll
View File

@ -1842,23 +1842,23 @@ entry:
; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.10, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.10, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.11, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[SCRATCHREG:[0-9]+]] = LWZtoc %const.11, $r2 :: (load 4 from got)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 56, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 56, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 60, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 60, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 64, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 64, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 68, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 68, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 72, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 72, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 76, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 76, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 80, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 80, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[SCRATCHREG:[0-9]+]], 84, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[SCRATCHREG:[0-9]+]], 84, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 88, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 88, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 92, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 92, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 96, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 96, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 100, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 100, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 104, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 104, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 108, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 108, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 112, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 112, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 116, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 116, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 120, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 120, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 124, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 124, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 128, $r1 :: (store 4) ; 32BIT-DAG: STW killed renamable $r[[SCRATCHREG:[0-9]+]], 128, $r1 :: (store 4)
; 32BIT-DAG: renamable $r[[REGF1:[0-9]+]] = LWZtoc @f14, $r2 :: (load 4 from got) ; 32BIT-DAG: renamable $r[[REGF1:[0-9]+]] = LWZtoc @f14, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGF1]] :: (load 4 from @f14) ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGF1]] :: (load 4 from @f14)
@ -2243,33 +2243,33 @@ define void @caller_mix() {
; 32BIT-DAG: $r9 = LI 7 ; 32BIT-DAG: $r9 = LI 7
; 32BIT-DAG: $r10 = LI 8 ; 32BIT-DAG: $r10 = LI 8
; 32BIT-DAG: STW killed renamable $r[[REG1:[0-9]+]], 56, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG1:[0-9]+]], 56, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG2:[0-9]+]], 60, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG2:[0-9]+]], 60, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG3:[0-9]+]], 64, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG3:[0-9]+]], 64, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG4:[0-9]+]], 68, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG4:[0-9]+]], 68, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG5:[0-9]+]], 72, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG5:[0-9]+]], 72, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG6:[0-9]+]], 76, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG6:[0-9]+]], 76, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG7:[0-9]+]], 80, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG7:[0-9]+]], 80, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG8:[0-9]+]], 84, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG8:[0-9]+]], 84, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG9:[0-9]+]], 88, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG9:[0-9]+]], 88, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG10:[0-9]+]], 92, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG10:[0-9]+]], 92, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG11:[0-9]+]], 96, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG11:[0-9]+]], 96, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG12:[0-9]+]], 100, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG12:[0-9]+]], 100, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG13:[0-9]+]], 104, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG13:[0-9]+]], 104, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG14:[0-9]+]], 108, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG14:[0-9]+]], 108, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG15:[0-9]+]], 112, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG15:[0-9]+]], 112, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG16:[0-9]+]], 116, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG16:[0-9]+]], 116, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG17:[0-9]+]], 120, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG17:[0-9]+]], 120, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG18:[0-9]+]], 128, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG18:[0-9]+]], 128, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW renamable $r[[REG19:[0-9]+]], 124, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW renamable $r[[REG19:[0-9]+]], 124, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG20:[0-9]+]], 132, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[REG20:[0-9]+]], 132, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG21:[0-9]+]], 136, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG21:[0-9]+]], 136, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG22:[0-9]+]], 140, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[REG22:[0-9]+]], 140, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG23:[0-9]+]], 144, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG23:[0-9]+]], 144, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG24:[0-9]+]], 148, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[REG24:[0-9]+]], 148, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG25:[0-9]+]], 152, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG25:[0-9]+]], 152, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG26:[0-9]+]], 156, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[REG26:[0-9]+]], 156, $r1 :: (store 4 + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG27:[0-9]+]], 160, $r1 :: (store 4, align 8) ; 32BIT-DAG: STW killed renamable $r[[REG27:[0-9]+]], 160, $r1 :: (store 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REG28:[0-9]+]], 164, $r1 :: (store 4 + 4) ; 32BIT-DAG: STW killed renamable $r[[REG28:[0-9]+]], 164, $r1 :: (store 4 + 4, align 8)
; 32BIT-NEXT: BL_NOP <mcsymbol .mix_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $r3 ; 32BIT-NEXT: BL_NOP <mcsymbol .mix_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $r3
; 32BIT-NEXT: ADJCALLSTACKUP 168, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 168, 0, implicit-def dead $r1, implicit $r1