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[X86][SSE41] Added test cases for improving insertps shuffles
As mentioned on D14261, an upcoming patch will improve combines of insertps instructions. llvm-svn: 256706
This commit is contained in:
Simon Pilgrim
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111
test/CodeGen/X86/insertps-combine.ll
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111
test/CodeGen/X86/insertps-combine.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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define <4 x float> @shuffle_v4f32_0z27(<4 x float> %x, <4 x float> %a) {
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; SSE-LABEL: shuffle_v4f32_0z27:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm2, %xmm2
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; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[2]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z27:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[2]
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
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%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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%vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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ret <4 x float> %vecinit5
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}
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define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %xyzw, <4 x float> %abcd) {
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; SSE-LABEL: shuffle_v4f32_0zz4:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm2, %xmm2
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; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0zz4:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %xyzw, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
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%vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuffle_v4f32_0z24(<4 x float> %xyzw, <4 x float> %abcd) {
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; SSE-LABEL: shuffle_v4f32_0z24:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm2, %xmm2
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; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z24:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3]
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %xyzw, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %xyzw, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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%vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit5
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}
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define <4 x float> @shuffle_v4f32_0zz0(float %a) {
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; SSE-LABEL: shuffle_v4f32_0zz0:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,1,0]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0zz0:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,0]
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; AVX-NEXT: retq
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%vecinit = insertelement <4 x float> undef, float %a, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
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%vecinit3 = insertelement <4 x float> %vecinit2, float %a, i32 3
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ret <4 x float> %vecinit3
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}
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define <4 x float> @shuffle_v4f32_0z6z(<4 x float> %A, <4 x float> %B) {
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; SSE-LABEL: shuffle_v4f32_0z6z:
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; SSE: # BB#0:
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z6z:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %A, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecext2 = extractelement <4 x float> %B, i32 2
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%vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
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ret <4 x float> %vecinit4
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}
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