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[MachineIRBuilder] Add buildOr helper. NFC.
This isn't used anywhere yet, but I need it for a future commit. llvm-svn: 307141
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@ -296,6 +296,19 @@ public:
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MachineInstrBuilder buildAnd(unsigned Res, unsigned Op0,
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MachineInstrBuilder buildAnd(unsigned Res, unsigned Op0,
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unsigned Op1);
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unsigned Op1);
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/// Build and insert \p Res<def> = G_OR \p Op0, \p Op1
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///
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/// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
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/// Op1.
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///
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/// \pre setBasicBlock or setMI must have been called.
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/// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
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/// with the same (scalar or vector) type).
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildOr(unsigned Res, unsigned Op0,
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unsigned Op1);
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/// Build and insert \p Res<def> = G_ANYEXT \p Op0
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/// Build and insert \p Res<def> = G_ANYEXT \p Op0
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///
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///
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/// G_ANYEXT produces a register of the specified width, with bits 0 to
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/// G_ANYEXT produces a register of the specified width, with bits 0 to
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@ -240,6 +240,10 @@ MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
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return buildBinaryOp(TargetOpcode::G_AND, Res, Op0, Op1);
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return buildBinaryOp(TargetOpcode::G_AND, Res, Op0, Op1);
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}
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}
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MachineInstrBuilder MachineIRBuilder::buildOr(unsigned Res, unsigned Op0,
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unsigned Op1) {
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return buildBinaryOp(TargetOpcode::G_OR, Res, Op0, Op1);
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}
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MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
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MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
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return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
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return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
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