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Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.

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llvm-svn: 138840
This commit is contained in:
Owen Anderson 2011-08-30 22:58:27 +00:00
parent a59d489162
commit adac5b2109
3 changed files with 44 additions and 30 deletions
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4
lib/Target/ARM/ARMInstrThumb2.td
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@ -19,7 +19,6 @@ def it_pred_asmoperand : AsmOperandClass {
def it_pred : Operand<i32> { def it_pred : Operand<i32> {
let PrintMethod = "printMandatoryPredicateOperand"; let PrintMethod = "printMandatoryPredicateOperand";
let ParserMatchClass = it_pred_asmoperand; let ParserMatchClass = it_pred_asmoperand;
let DecoderMethod = "DecodeITCond";
} }
// IT block condition mask // IT block condition mask
@ -27,7 +26,6 @@ def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
def it_mask : Operand<i32> { def it_mask : Operand<i32> {
let PrintMethod = "printThumbITMask"; let PrintMethod = "printThumbITMask";
let ParserMatchClass = it_mask_asmoperand; let ParserMatchClass = it_mask_asmoperand;
let DecoderMethod = "DecodeITMask";
} }
// Shifted operands. No register controlled shifts for Thumb2. // Shifted operands. No register controlled shifts for Thumb2.
@ -3013,6 +3011,8 @@ def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
bits<4> mask; bits<4> mask;
let Inst{7-4} = cc; let Inst{7-4} = cc;
let Inst{3-0} = mask; let Inst{3-0} = mask;
let DecoderMethod = "DecodeIT";
} }
// Branch and Exchange Jazelle -- for disassembly only // Branch and Exchange Jazelle -- for disassembly only

58
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -230,9 +230,7 @@ static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val, static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc" #include "ARMGenDisassemblerTables.inc"
@ -480,18 +478,20 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
// code and mask operands so that we can apply them correctly // code and mask operands so that we can apply them correctly
// to the subsequent instructions. // to the subsequent instructions.
if (MI.getOpcode() == ARM::t2IT) { if (MI.getOpcode() == ARM::t2IT) {
// (3 - the number of trailing zeros) is the number of then / else.
unsigned firstcond = MI.getOperand(0).getImm(); unsigned firstcond = MI.getOperand(0).getImm();
uint32_t mask = MI.getOperand(1).getImm(); unsigned Mask = MI.getOperand(1).getImm();
unsigned zeros = CountTrailingZeros_32(mask); unsigned CondBit0 = Mask >> 4 & 1;
mask >>= zeros+1; unsigned NumTZ = CountTrailingZeros_32(Mask);
assert(NumTZ <= 3 && "Invalid IT mask!");
for (unsigned i = 0; i < 4 - (zeros+1); ++i) { for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
if (firstcond ^ (mask & 1)) bool T = ((Mask >> Pos) & 1) == CondBit0;
ITBlock.push_back(firstcond ^ 1); if (T)
ITBlock.insert(ITBlock.begin(), firstcond);
else else
ITBlock.push_back(firstcond); ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
mask >>= 1;
} }
ITBlock.push_back(firstcond); ITBlock.push_back(firstcond);
} }
@ -3109,7 +3109,7 @@ static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
} }
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align)); Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else else
@ -3345,26 +3345,28 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
return S; return S;
} }
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond, static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = Success; DecodeStatus S = Success;
if (Cond == 0xF) { unsigned pred = fieldFromInstruction16(Insn, 4, 4);
Cond = 0xE; // The InstPrinter needs to have the low bit of the predicate in
// the mask operand to be able to print it properly.
unsigned mask = fieldFromInstruction16(Insn, 0, 5);
if (pred == 0xF) {
pred = 0xE;
CHECK(S, Unpredictable); CHECK(S, Unpredictable);
} }
Inst.addOperand(MCOperand::CreateImm(Cond)); if ((mask & 0xF) == 0) {
return S; // Preserve the high bit of the mask, which is the low bit of
} // the predicate.
mask &= 0x10;
static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask, mask |= 0x8;
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
if (Mask == 0) {
Mask = 0x8;
CHECK(S, Unpredictable); CHECK(S, Unpredictable);
} }
Inst.addOperand(MCOperand::CreateImm(Mask));
Inst.addOperand(MCOperand::CreateImm(pred));
Inst.addOperand(MCOperand::CreateImm(mask));
return S; return S;
} }

12
test/MC/Disassembler/ARM/thumb2.txt
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@ -39,3 +39,15 @@
0x00 0xbf 0x00 0xbf
0xf5 0x1b 0xf5 0x1b
0x11 0x1d 0x11 0x1d
# CHECK: ittee ls
# CHECK: addls r0, r1, r2
# CHECK: nopls
# CHECK: subhi r5, r6, r7
# CHECK: addhi r1, r2, #4
0x99 0xbf
0x88 0x18
0x00 0xbf
0xf5 0x1b
0x11 0x1d