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[ARM] VECTOR_REG_CAST undef -> undef

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Propagate undef through VECTOR_REG_CAST nodes, allowing extra
simplification in some patterns.
This commit is contained in:
David Green 2021-02-28 11:13:49 +00:00
parent 510612328d
commit ae50d26182
2 changed files with 13 additions and 0 deletions
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4
lib/Target/ARM/ARMISelLowering.cpp
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@ -14020,6 +14020,10 @@ PerformVECTOR_REG_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
if (ST->isLittle())
return DCI.DAG.getNode(ISD::BITCAST, dl, VT, Op);
// VECTOR_REG_CAST undef -> undef
if (Op.isUndef())
return DCI.DAG.getUNDEF(VT);
// VECTOR_REG_CAST(VECTOR_REG_CAST(x)) == VECTOR_REG_CAST(x)
if (Op->getOpcode() == ARMISD::VECTOR_REG_CAST) {
// If the valuetypes are the same, we can remove the cast entirely.

9
test/CodeGen/Thumb2/mve-be.ll
View File

@ -355,4 +355,13 @@ entry:
ret void
}
define arm_aapcs_vfpcc <8 x half> @undef_one() {
; CHECK-LABEL: undef_one:
; CHECK: @ %bb.0:
; CHECK-NEXT: bx lr
%c = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v4f32(<4 x float> undef)
ret <8 x half> %c
}
declare <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v4f32(<4 x float>)
declare <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v4i32(<4 x i32>)