mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 03:53:04 +02:00
Refactor cmov selection code out to a separate function. No functionality change.
llvm-svn: 89396
This commit is contained in:
Evan Cheng
parent
141e028b96
commit
af22254deb
@ -149,6 +149,9 @@ private:
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/// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
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SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
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/// SelectCMOVOp - Select CMOV instructions for ARM.
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SDNode *SelectCMOVOp(SDValue Op);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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@ -1302,6 +1305,123 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
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EVT VT = Op.getValueType();
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2 = Op.getOperand(2);
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SDValue N3 = Op.getOperand(3);
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SDValue InFlag = Op.getOperand(4);
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assert(N2.getOpcode() == ISD::Constant);
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assert(N3.getOpcode() == ISD::Register);
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if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
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// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 18 cost = 1 size = 0
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SDValue CPTmp0;
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (Subtarget->isThumb()) {
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if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
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unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
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unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
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unsigned Opc = 0;
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switch (SOShOp) {
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case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
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case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
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case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
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case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
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default:
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llvm_unreachable("Unknown so_reg opcode!");
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break;
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}
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SDValue SOShImm =
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CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
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}
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} else {
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if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCs, MVT::i32, Ops, 7);
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}
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false,
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// (imm:i32)<<P:Predicate_so_imm>>:$true,
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// (imm:i32):$cc)
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// Emits: (MOVCCi:i32 GPR:i32:$false,
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// (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
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// Pattern complexity = 10 cost = 1 size = 0
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if (N3.getOpcode() == ISD::Constant) {
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if (Subtarget->isThumb()) {
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if (Predicate_t2_so_imm(N3.getNode())) {
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SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getZExtValue()),
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MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::t2MOVCCi, MVT::i32, Ops, 5);
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}
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} else {
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if (Predicate_so_imm(N3.getNode())) {
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SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getZExtValue()),
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MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCi, MVT::i32, Ops, 5);
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}
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}
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}
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 1 size = 0
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//
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 11 size = 0
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//
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// Also FCPYScc and FCPYDcc.
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
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unsigned Opc = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: assert(false && "Illegal conditional move type!");
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break;
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case MVT::i32:
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Opc = Subtarget->isThumb()
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? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
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: ARM::MOVCCr;
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break;
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case MVT::f32:
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Opc = ARM::VMOVScc;
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break;
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case MVT::f64:
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Opc = ARM::VMOVDcc;
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break;
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}
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
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}
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SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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@ -1549,122 +1669,8 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDValue(Chain.getNode(), Chain.getResNo()));
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return NULL;
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}
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case ARMISD::CMOV: {
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EVT VT = Op.getValueType();
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2 = Op.getOperand(2);
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SDValue N3 = Op.getOperand(3);
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SDValue InFlag = Op.getOperand(4);
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assert(N2.getOpcode() == ISD::Constant);
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assert(N3.getOpcode() == ISD::Register);
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if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
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// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 18 cost = 1 size = 0
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SDValue CPTmp0;
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (Subtarget->isThumb()) {
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if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
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unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
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unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
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unsigned Opc = 0;
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switch (SOShOp) {
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case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
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case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
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case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
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case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
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default:
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llvm_unreachable("Unknown so_reg opcode!");
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break;
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}
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SDValue SOShImm =
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CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
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}
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} else {
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if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCs, MVT::i32, Ops, 7);
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}
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false,
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// (imm:i32)<<P:Predicate_so_imm>>:$true,
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// (imm:i32):$cc)
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// Emits: (MOVCCi:i32 GPR:i32:$false,
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// (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
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// Pattern complexity = 10 cost = 1 size = 0
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if (N3.getOpcode() == ISD::Constant) {
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if (Subtarget->isThumb()) {
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if (Predicate_t2_so_imm(N3.getNode())) {
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SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getZExtValue()),
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MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::t2MOVCCi, MVT::i32, Ops, 5);
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}
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} else {
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if (Predicate_so_imm(N3.getNode())) {
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SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getZExtValue()),
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MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCi, MVT::i32, Ops, 5);
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}
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}
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}
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 1 size = 0
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//
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// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
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// Pattern complexity = 6 cost = 11 size = 0
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//
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// Also FCPYScc and FCPYDcc.
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
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unsigned Opc = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: assert(false && "Illegal conditional move type!");
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break;
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case MVT::i32:
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Opc = Subtarget->isThumb()
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? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
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: ARM::MOVCCr;
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break;
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case MVT::f32:
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Opc = ARM::VMOVScc;
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break;
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case MVT::f64:
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Opc = ARM::VMOVDcc;
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break;
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}
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
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}
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case ARMISD::CMOV:
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return SelectCMOVOp(Op);
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case ARMISD::CNEG: {
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EVT VT = Op.getValueType();
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SDValue N0 = Op.getOperand(0);
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