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[Hexagon] Fixes/changes to instruction selection
- Add patterns for rr/abs addressing modes. - Set addrMode to PostInc where necessary. - Misc fixes. llvm-svn: 275574
This commit is contained in:
Krzysztof Parzyszek
parent
f9a637b0bf
commit
af2caac28b
@ -2052,7 +2052,7 @@ let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
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}
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// Load / Post increment circular addressing mode.
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let Uses = [CS], hasSideEffects = 0 in
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let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in
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class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
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: LDInst <(outs RC:$dst, IntRegs:$_dst_),
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(ins IntRegs:$Rz, ModRegs:$Mu),
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@ -2099,7 +2099,7 @@ let accessSize = DoubleWordAccess in
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def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
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// Load / Post increment circular addressing mode.
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let Uses = [CS], hasSideEffects = 0 in
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let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in
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class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
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: LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
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(ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
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@ -2128,7 +2128,7 @@ def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>;
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//===----------------------------------------------------------------------===//
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// Circular loads with immediate offset.
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//===----------------------------------------------------------------------===//
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let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in
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let Uses = [CS], mayLoad = 1, hasSideEffects = 0, addrMode = PostInc in
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class T_load_pci <string mnemonic, RegisterClass RC,
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Operand ImmOp, bits<4> MajOp>
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: LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
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@ -2240,7 +2240,7 @@ def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
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//===----------------------------------------------------------------------===//
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// Bit-reversed loads with auto-increment register
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in
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let hasSideEffects = 0, addrMode = PostInc in
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class T_load_pbr<string mnemonic, RegisterClass RC,
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MemAccessSize addrSize, bits<4> majOp>
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: LDInst
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@ -3609,7 +3609,8 @@ multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
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// swapped. This relies on the knowledge that the F.Fragment uses names
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// "ptr" and "val".
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class SwapSt<PatFrag F>
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: PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
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: PatFrag<(ops node:$val, node:$ptr), F.Fragment, F.PredicateCode,
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F.OperandTransform>;
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let AddedComplexity = 20 in {
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defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>;
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@ -3673,7 +3674,7 @@ def S2_allocframe: ST0Inst <
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// S2_storer[bhwdf]_pci: Store byte/half/word/double.
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// S2_storer[bhwdf]_pci -> S2_storerbnew_pci
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let Uses = [CS] in
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let Uses = [CS], addrMode = PostInc in
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class T_store_pci <string mnemonic, RegisterClass RC,
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Operand Imm, bits<4>MajOp,
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MemAccessSize AlignSize, string RegSrc = "Rt">
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@ -3716,7 +3717,8 @@ def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
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def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
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DoubleWordAccess>;
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let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in
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let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4,
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addrMode = PostInc in
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class T_storenew_pci <string mnemonic, Operand Imm,
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bits<2>MajOp, MemAccessSize AlignSize>
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: NVInst < (outs IntRegs:$_dst_),
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@ -3752,7 +3754,7 @@ def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
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//===----------------------------------------------------------------------===//
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// Circular stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let Uses = [CS] in
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let Uses = [CS], addrMode = PostInc in
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class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
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MemAccessSize AlignSize, string RegSrc = "Rt">
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: STInst <(outs IntRegs:$_dst_),
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@ -3788,7 +3790,8 @@ def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
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//===----------------------------------------------------------------------===//
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// Circular .new stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
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let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
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addrMode = PostInc in
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class T_storenew_pcr <string mnemonic, bits<2>MajOp,
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MemAccessSize AlignSize>
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: NVInst <(outs IntRegs:$_dst_),
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@ -3819,7 +3822,7 @@ def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
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//===----------------------------------------------------------------------===//
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// Bit-reversed stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in
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let hasSideEffects = 0, addrMode = PostInc in
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class T_store_pbr<string mnemonic, RegisterClass RC,
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MemAccessSize addrSize, bits<3> majOp,
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bit isHalf = 0>
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@ -3864,7 +3867,7 @@ def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
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// Bit-reversed .new stores with auto-increment register
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//===----------------------------------------------------------------------===//
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let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
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hasSideEffects = 0 in
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hasSideEffects = 0, addrMode = PostInc in
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class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
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: NVInst <(outs IntRegs:$_dst_),
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(ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
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@ -4741,10 +4744,10 @@ def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
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// HI/LO Instructions
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let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
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hasNewValue = 1, opNewValue = 0 in
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class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp>
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class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp>
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: ALU32_ri<(outs IntRegs:$dst),
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(ins i32imm:$imm_value),
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"$dst"#RegHalf#" = #"#Op#"($imm_value)", []> {
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(ins u16Imm:$imm_value),
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"$dst"#RegHalf#" = $imm_value", []> {
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bits<5> dst;
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bits<32> imm_value;
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let IClass = 0b0111;
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@ -4753,15 +4756,13 @@ class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp>
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let Inst{26-24} = MajOp;
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let Inst{21} = MinOp;
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let Inst{20-16} = dst;
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let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30});
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let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16});
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let Inst{23-22} = imm_value{15-14};
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let Inst{13-0} = imm_value{13-0};
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}
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let isAsmParserOnly = 1 in {
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def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>;
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def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>;
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def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>;
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def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>;
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def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>;
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def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>;
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}
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let isMoveImm = 1, isCodeGenOnly = 1 in
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@ -4828,7 +4829,7 @@ def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "",
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let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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isCodeGenOnly = 1 in
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def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)",
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def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "",
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[(set (i1 PredRegs:$dst), 0)]>;
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// Pseudo instructions.
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@ -1047,6 +1047,18 @@ let AddedComplexity = 40 in {
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def: Storexs_pat<store, I64, S4_storerd_rr>;
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}
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class Store_rr_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
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: Pat<(Store Value:$Ru, (add I32:$Rs, I32:$Rt)),
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(MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>;
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let AddedComplexity = 20 in {
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def: Store_rr_pat<truncstorei8, I32, S4_storerb_rr>;
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def: Store_rr_pat<truncstorei16, I32, S4_storerh_rr>;
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def: Store_rr_pat<store, I32, S4_storeri_rr>;
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def: Store_rr_pat<store, I64, S4_storerd_rr>;
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}
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// memd(Rx++#s4:3)=Rtt
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// memd(Rx++#s4:3:circ(Mu))=Rtt
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// memd(Rx++I:circ(Mu))=Rtt
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@ -1733,7 +1745,7 @@ class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
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: NVInst_V4<(outs),
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(ins IntRegs:$src1, brtarget:$offset),
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"if ("#!if(isNegCond, "!","")#mnemonic
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#"($src1.new, #"#ImmVal#")) jump:"
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#"($src1.new, #" # ImmVal # ")) jump:"
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#!if(isTak, "t","nt")#" $offset", []> {
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let isTaken = isTak;
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@ -2822,13 +2834,13 @@ def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
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//===----------------------------------------------------------------------===//
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def m5Imm8Pred : PatLeaf<(i32 imm), [{
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int32_t v = (int8_t)N->getSExtValue();
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return v >= -32 && v <= -1;
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int8_t v = (int8_t)N->getSExtValue();
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return v > -32 && v <= -1;
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}]>;
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def m5Imm16Pred : PatLeaf<(i32 imm), [{
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int32_t v = (int16_t)N->getSExtValue();
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return v >= -32 && v <= -1;
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int16_t v = (int16_t)N->getSExtValue();
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return v > -32 && v <= -1;
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}]>;
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def Clr5Imm8Pred : PatLeaf<(i32 imm), [{
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@ -3193,7 +3205,7 @@ let AddedComplexity = 200 in {
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/*sext*/ Clr5Imm16, L4_iand_memoph_io>;
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defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, and, Clr5Imm16Pred,
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/*zext*/ Clr5Imm16, L4_iand_memoph_io>;
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defm: Memopxi_pat<load, store, u6_2ImmPred, and, Clr5ImmPred, Clr5Imm16,
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defm: Memopxi_pat<load, store, u6_2ImmPred, and, Clr5ImmPred, Clr5Imm32,
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L4_iand_memopw_io>;
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// setbit imm
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@ -3343,6 +3355,7 @@ defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
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let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
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Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
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let isExtended = 1, opExtendable = 0 in
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def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
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@ -3689,6 +3702,17 @@ class Stoream_pat<PatFrag Store, PatFrag Value, PatFrag Addr, PatFrag ValueMod,
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: Pat<(Store Value:$val, Addr:$addr),
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(MI Addr:$addr, (ValueMod Value:$val))>;
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let AddedComplexity = 30 in {
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def: Storea_pat<truncstorei8, I32, addrga, S2_storerbabs>;
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def: Storea_pat<truncstorei16, I32, addrga, S2_storerhabs>;
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def: Storea_pat<store, I32, addrga, S2_storeriabs>;
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def: Storea_pat<store, I64, addrga, S2_storerdabs>;
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def: Stoream_pat<truncstorei8, I64, addrga, LoReg, S2_storerbabs>;
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def: Stoream_pat<truncstorei16, I64, addrga, LoReg, S2_storerhabs>;
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def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
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}
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def: Storea_pat<SwapSt<atomic_store_8>, I32, addrgp, S2_storerbgp>;
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def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhgp>;
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def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storerigp>;
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@ -3826,6 +3850,26 @@ defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
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let accessSize = DoubleWordAccess in
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defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
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class LoadAbs_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
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: Pat <(VT (ldOp (HexagonCONST32 tglobaladdr:$absaddr))),
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(VT (MI tglobaladdr:$absaddr))>;
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let AddedComplexity = 30 in {
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def: LoadAbs_pats <load, L4_loadri_abs>;
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def: LoadAbs_pats <zextloadi1, L4_loadrub_abs>;
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def: LoadAbs_pats <sextloadi8, L4_loadrb_abs>;
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def: LoadAbs_pats <extloadi8, L4_loadrub_abs>;
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def: LoadAbs_pats <zextloadi8, L4_loadrub_abs>;
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def: LoadAbs_pats <sextloadi16, L4_loadrh_abs>;
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def: LoadAbs_pats <extloadi16, L4_loadruh_abs>;
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def: LoadAbs_pats <zextloadi16, L4_loadruh_abs>;
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def: LoadAbs_pats <load, L4_loadrd_abs, i64>;
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}
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let AddedComplexity = 30 in
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def: Pat<(i64 (zextloadi1 (HexagonCONST32 tglobaladdr:$absaddr))),
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(Zext64 (L4_loadrub_abs tglobaladdr:$absaddr))>;
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//===----------------------------------------------------------------------===//
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// multiclass for load instructions with GP-relative addressing mode.
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// Rx=mem[bhwd](##global)
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