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- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.

Browse Source 
- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808
This commit is contained in:
Evan Cheng 2008-11-06 17:48:05 +00:00
parent 1ea366a419
commit af54e4ed18
4 changed files with 48 additions and 76 deletions
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24
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -248,7 +248,7 @@ void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
}
void ARMCodeEmitter::emitWordLE(unsigned Binary) {
DOUT << "\t" << (void*)Binary << "\n";
DOUT << " " << (void*)Binary << "\n";
MCE.emitWordLE(Binary);
}
@ -282,10 +282,10 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
case ARMII::MulFrm:
emitMulFrmInstruction(MI);
break;
case ARMII::Branch:
case ARMII::BrFrm:
emitBranchInstruction(MI);
break;
case ARMII::BranchMisc:
case ARMII::BrMiscFrm:
emitMiscBranchInstruction(MI);
break;
}
@ -305,7 +305,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
ARMConstantPoolValue *ACPV =
static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
DOUT << "\t** ARM constant pool #" << CPI << " @ "
DOUT << " ** ARM constant pool #" << CPI << " @ "
<< (void*)MCE.getCurrentPCValue() << " " << *ACPV << "\n";
GlobalValue *GV = ACPV->getGV();
@ -322,7 +322,7 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
} else {
Constant *CV = MCPE.Val.ConstVal;
DOUT << "\t** Constant pool #" << CPI << " @ "
DOUT << " ** Constant pool #" << CPI << " @ "
<< (void*)MCE.getCurrentPCValue() << " " << *CV << "\n";
if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
@ -380,7 +380,7 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
}
void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
DOUT << "\t** LPC" << LabelID << " @ "
DOUT << " ** LPC" << LabelID << " @ "
<< (void*)MCE.getCurrentPCValue() << '\n';
JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
}
@ -566,8 +566,6 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@ -621,8 +619,6 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
unsigned ImplicitRn) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@ -751,6 +747,9 @@ void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::TPsoft)
abort(); // FIXME
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
@ -771,7 +770,10 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::BX)
if (TID.Opcode == ARM::BX ||
TID.Opcode == ARM::BR_JTr ||
TID.Opcode == ARM::BR_JTm ||
TID.Opcode == ARM::BR_JTadd)
abort(); // FIXME
// Part of binary is determined by TableGn.

56
lib/Target/ARM/ARMInstrFormats.td
View File

@ -21,8 +21,8 @@ class Format<bits<5> val> {
def Pseudo : Format<1>;
def MulFrm : Format<2>;
def Branch : Format<3>;
def BranchMisc : Format<4>;
def BrFrm : Format<3>;
def BrMiscFrm : Format<4>;
def DPFrm : Format<5>;
def DPSoRegFrm : Format<6>;
@ -134,40 +134,25 @@ class AXI<dag oops, dag iops, Format f, string asm,
"", pattern>;
// Ctrl flow instructions
class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
class ABI<bits<4> opcod, dag oops, dag iops, string opc,
string asm, list<dag> pattern>
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
asm,"",pattern> {
let Inst{27-24} = opcod;
}
class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
"", pattern> {
let Inst{27-24} = opcod;
}
// FIXME: BX
class AXIx2<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
"", pattern>;
class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{27-24} = opcod;
}
class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern> {
let Inst{27-24} = opcod;
}
// BR_JT instructions
// == mov pc
class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
asm, "", pattern> {
let Inst{20} = 0; // S Bit
let Inst{24-21} = opcod;
@ -175,7 +160,7 @@ class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
}
// == add pc
class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
: XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm,
asm, "", pattern> {
let Inst{20} = 0; // S bit
let Inst{24-21} = opcod;
@ -183,7 +168,7 @@ class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
}
// == ldr pc
class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
: XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm,
asm, "", pattern> {
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
@ -641,29 +626,14 @@ class AI3sthpo<dag oops, dag iops, Format f, string opc,
// addrmode4 instructions
class AI4<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern>
: I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> {
let Inst{25-27} = {0,0,1};
}
class AXI4ld<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{22} = 0; // S bit
let Inst{27-25} = 0b100;
}
class AXI4ldpc<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 1; // L bit
let Inst{27-25} = 0b100;
}
class AXI4st<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
: XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> {
let Inst{20} = 0; // L bit

4
lib/Target/ARM/ARMInstrInfo.h
View File

@ -79,8 +79,8 @@ namespace ARMII {
MulFrm = 2 << FormShift,
// Branch instructions
Branch = 3 << FormShift,
BranchMisc = 4 << FormShift,
BrFrm = 3 << FormShift,
BrMiscFrm = 4 << FormShift,
// Data Processing instructions
DPFrm = 5 << FormShift,

40
lib/Target/ARM/ARMInstrInfo.td
View File

@ -445,7 +445,7 @@ multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
let isNotDuplicable = 1 in
def CONSTPOOL_ENTRY :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size),
i32imm:$size),
"${instid:label} ${cpidx:cpentry}", []>;
let Defs = [SP], Uses = [SP] in {
@ -465,6 +465,8 @@ PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
// Address computation and loads and stores in PIC mode.
let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
@ -505,14 +507,14 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
}
}
} // isNotDuplicable = 1
//===----------------------------------------------------------------------===//
// Control Flow Instructions.
//
let isReturn = 1, isTerminator = 1 in
def BX_RET : AI<(outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]> {
def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
let Inst{7-4} = 0b0001;
let Inst{19-8} = 0b111111111111;
let Inst{27-20} = 0b00010010;
@ -521,8 +523,9 @@ let isReturn = 1, isTerminator = 1 in
// FIXME: remove when we have a way to marking a MI with these properties.
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
// FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1 in
def LDM_RET : AXI4ldpc<(outs),
def LDM_RET : AXI4ld<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
[]>;
@ -530,16 +533,16 @@ let isReturn = 1, isTerminator = 1 in
let isCall = 1,
Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
def BL : ABLI<0b1011, (outs), (ins i32imm:$func, variable_ops), Branch,
def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
"bl ${func:call}",
[(ARMcall tglobaladdr:$func)]>;
def BL_pred : ABLpredI<0b1011, (outs), (ins i32imm:$func, variable_ops), Branch,
def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
"bl", " ${func:call}",
[(ARMcall_pred tglobaladdr:$func)]>;
// ARMv5T and above
def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BranchMisc,
def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
"blx $func",
[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
let Inst{7-4} = 0b0011;
@ -549,9 +552,9 @@ let isCall = 1,
let Uses = [LR] in {
// ARMv4T
def BX : AXIx2<(outs), (ins GPR:$func, variable_ops),
BranchMisc, "mov lr, pc\n\tbx $func",
[(ARMcall_nolink GPR:$func)]>;
def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
"mov lr, pc\n\tbx $func",
[(ARMcall_nolink GPR:$func)]>;
}
}
@ -559,7 +562,7 @@ let isBranch = 1, isTerminator = 1 in {
// B is "predicable" since it can be xformed into a Bcc.
let isBarrier = 1 in {
let isPredicable = 1 in
def B : ABI<0b1010, (outs), (ins brtarget:$target), Branch, "b $target",
def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
[(br bb:$target)]>;
let isNotDuplicable = 1, isIndirectBranch = 1 in {
@ -583,7 +586,7 @@ let isBranch = 1, isTerminator = 1 in {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
def Bcc : ABccI<0b1010, (outs), (ins brtarget:$target), Branch,
def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
"b", " $target",
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
}
@ -909,12 +912,12 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm),
//
def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
"mul", " $dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
"mul", " $dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
"mla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
"mla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
// Extra precision multiplies with low / high results
def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
@ -963,7 +966,6 @@ def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
let Inst{7-4} = 0b1101;
}
// FIXME: encoding
multiclass AI_smul<string opc, PatFrag opnode> {
def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "bb"), " $dst, $a, $b",
@ -1021,7 +1023,6 @@ multiclass AI_smul<string opc, PatFrag opnode> {
}
// FIXME: encoding
multiclass AI_smla<string opc, PatFrag opnode> {
def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
@ -1142,7 +1143,6 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
(and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
(PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
//===----------------------------------------------------------------------===//
// Comparison Instructions...
//
@ -1215,7 +1215,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred
// __aeabi_read_tp preserves the registers r1-r3.
let isCall = 1,
Defs = [R0, R12, LR, CPSR] in {
def TPsoft : AXI<(outs), (ins), BranchMisc,
def TPsoft : ABXI<0b1011, (outs), (ins),
"bl __aeabi_read_tp",
[(set R0, ARMthread_pointer)]>;
}