RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 13:11:39 +01:00
Code Issues Projects Releases Wiki Activity

[AMDGPU] Refactor DPPCombine

Browse Source 
NFC. Extract IsShrinkable into a helper function, and
make Subtarget a member variable.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D99099

Change-Id: If4bc97a88a9ae4eb1df47e717345d46a6ed515bf
This commit is contained in:
Joe Nash 2021-03-22 14:34:55 -04:00
parent 8a90bdff9c
commit af64dca8a0
1 changed files with 50 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
lib/Target/AMDGPU/GCNDPPCombine.cpp
View File

@ -54,21 +54,20 @@ namespace {
class GCNDPPCombine : public MachineFunctionPass {
MachineRegisterInfo *MRI;
const SIInstrInfo *TII;
const GCNSubtarget *ST;
using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
MachineInstr *createDPPInst(MachineInstr &OrigMI,
MachineInstr &MovMI,
MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
RegSubRegPair CombOldVGPR,
MachineOperand *OldOpnd,
bool CombBCZ) const;
MachineOperand *OldOpnd, bool CombBCZ,
bool IsShrinkable) const;
MachineInstr *createDPPInst(MachineInstr &OrigMI,
MachineInstr &MovMI,
RegSubRegPair CombOldVGPR,
bool CombBCZ) const;
MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
RegSubRegPair CombOldVGPR, bool CombBCZ,
bool IsShrinkable) const;
bool hasNoImmOrEqual(MachineInstr &MI,
unsigned OpndName,
@ -99,7 +98,8 @@ public:
}
private:
int getDPPOp(unsigned Op) const;
int getDPPOp(unsigned Op, bool IsShrinkable) const;
bool isShrinkable(MachineInstr &OrigMI, unsigned OrigOp) const;
};
} // end anonymous namespace
@ -114,11 +114,32 @@ FunctionPass *llvm::createGCNDPPCombinePass() {
return new GCNDPPCombine();
}
int GCNDPPCombine::getDPPOp(unsigned Op) const {
bool GCNDPPCombine::isShrinkable(MachineInstr &OrigMI, unsigned OrigOp) const {
if (!TII->isVOP3(OrigOp)) {
return false;
}
if (!TII->hasVALU32BitEncoding(OrigOp)) {
LLVM_DEBUG(dbgs() << " Inst hasn't e32 equivalent\n");
return false;
}
// check if other than abs|neg modifiers are set (opsel for example)
const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {
LLVM_DEBUG(dbgs() << " Inst has non-default modifiers\n");
return false;
}
return true;
}
int GCNDPPCombine::getDPPOp(unsigned Op, bool IsShrinkable) const {
auto DPP32 = AMDGPU::getDPPOp32(Op);
if (DPP32 == -1) {
if (IsShrinkable) {
assert(DPP32 == -1);
auto E32 = AMDGPU::getVOPe32(Op);
DPP32 = (E32 == -1)? -1 : AMDGPU::getDPPOp32(E32);
DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32);
}
return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32;
}
@ -151,12 +172,13 @@ MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
MachineInstr &MovMI,
RegSubRegPair CombOldVGPR,
bool CombBCZ) const {
bool CombBCZ,
bool IsShrinkable) const {
assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp ||
MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO);
auto OrigOp = OrigMI.getOpcode();
auto DPPOp = getDPPOp(OrigOp);
auto DPPOp = getDPPOp(OrigOp, IsShrinkable);
if (DPPOp == -1) {
LLVM_DEBUG(dbgs() << " failed: no DPP opcode\n");
return nullptr;
@ -314,11 +336,9 @@ static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
return false;
}
MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
MachineInstr &MovMI,
RegSubRegPair CombOldVGPR,
MachineOperand *OldOpndValue,
bool CombBCZ) const {
MachineInstr *GCNDPPCombine::createDPPInst(
MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
MachineOperand *OldOpndValue, bool CombBCZ, bool IsShrinkable) const {
assert(CombOldVGPR.Reg);
if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) {
auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
@ -338,7 +358,7 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
return nullptr;
}
}
return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ);
return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);
}
// returns true if MI doesn't have OpndName immediate operand or the
@ -503,21 +523,8 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
continue;
}
if (TII->isVOP3(OrigOp)) {
if (!TII->hasVALU32BitEncoding(OrigOp)) {
LLVM_DEBUG(dbgs() << " failed: VOP3 hasn't e32 equivalent\n");
break;
}
// check if other than abs|neg modifiers are set (opsel for example)
const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {
LLVM_DEBUG(dbgs() << " failed: VOP3 has non-default modifiers\n");
break;
}
} else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) {
bool IsShrinkable = isShrinkable(OrigMI, OrigOp);
if (!(IsShrinkable || TII->isVOP1(OrigOp) || TII->isVOP2(OrigOp))) {
LLVM_DEBUG(dbgs() << " failed: not VOP1/2/3\n");
break;
}
@ -542,7 +549,7 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
LLVM_DEBUG(dbgs() << " combining: " << OrigMI);
if (Use == Src0) {
if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
OldOpndValue, CombBCZ)) {
OldOpndValue, CombBCZ, IsShrinkable)) {
DPPMIs.push_back(DPPInst);
Rollback = false;
}
@ -553,8 +560,9 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
BB->insert(OrigMI, NewMI);
if (TII->commuteInstruction(*NewMI)) {
LLVM_DEBUG(dbgs() << " commuted: " << *NewMI);
if (auto *DPPInst = createDPPInst(*NewMI, MovMI, CombOldVGPR,
OldOpndValue, CombBCZ)) {
if (auto *DPPInst =
createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,
IsShrinkable)) {
DPPMIs.push_back(DPPInst);
Rollback = false;
}
@ -587,12 +595,12 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
}
bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
auto &ST = MF.getSubtarget<GCNSubtarget>();
if (!ST.hasDPP() || skipFunction(MF.getFunction()))
ST = &MF.getSubtarget<GCNSubtarget>();
if (!ST->hasDPP() || skipFunction(MF.getFunction()))
return false;
MRI = &MF.getRegInfo();
TII = ST.getInstrInfo();
TII = ST->getInstrInfo();
bool Changed = false;
for (auto &MBB : MF) {
@ -602,7 +610,7 @@ bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
Changed = true;
++NumDPPMovsCombined;
} else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) {
if (ST.has64BitDPP() && combineDPPMov(MI)) {
if (ST->has64BitDPP() && combineDPPMov(MI)) {
Changed = true;
++NumDPPMovsCombined;
} else {