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[DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectors

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SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927

llvm-svn: 285118
This commit is contained in:
Simon Pilgrim 2016-10-25 20:56:42 +00:00
parent 14476b73f7
commit afa4a638a1
2 changed files with 14 additions and 40 deletions
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6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2317,10 +2317,8 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
// If we know the sign bits of both operands are zero, strength reduce to a
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
if (!VT.isVector()) {
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
}
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
// fold (sdiv X, pow2) -> simple ops after legalize
// FIXME: We check for the exact bit here because the generic lowering gives

48
test/CodeGen/X86/combine-sdiv.ll
View File

@ -82,52 +82,28 @@ define <4 x i32> @combine_vec_sdiv_by_pos1(<4 x i32> %x) {
; SSE: # BB#0:
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: pextrd $1, %xmm0, %eax
; SSE-NEXT: movl %eax, %ecx
; SSE-NEXT: sarl $31, %ecx
; SSE-NEXT: shrl $30, %ecx
; SSE-NEXT: addl %eax, %ecx
; SSE-NEXT: sarl $2, %ecx
; SSE-NEXT: pextrd $2, %xmm0, %eax
; SSE-NEXT: shrl $2, %eax
; SSE-NEXT: pextrd $2, %xmm0, %ecx
; SSE-NEXT: pextrd $3, %xmm0, %edx
; SSE-NEXT: pinsrd $1, %ecx, %xmm0
; SSE-NEXT: movl %eax, %ecx
; SSE-NEXT: sarl $31, %ecx
; SSE-NEXT: shrl $29, %ecx
; SSE-NEXT: addl %eax, %ecx
; SSE-NEXT: sarl $3, %ecx
; SSE-NEXT: pinsrd $1, %eax, %xmm0
; SSE-NEXT: shrl $3, %ecx
; SSE-NEXT: pinsrd $2, %ecx, %xmm0
; SSE-NEXT: movl %edx, %eax
; SSE-NEXT: sarl $31, %eax
; SSE-NEXT: shrl $28, %eax
; SSE-NEXT: addl %edx, %eax
; SSE-NEXT: sarl $4, %eax
; SSE-NEXT: pinsrd $3, %eax, %xmm0
; SSE-NEXT: shrl $4, %edx
; SSE-NEXT: pinsrd $3, %edx, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sdiv_by_pos1:
; AVX: # BB#0:
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: sarl $31, %ecx
; AVX-NEXT: shrl $30, %ecx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm1
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $1, %eax, %xmm0, %xmm1
; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: sarl $31, %ecx
; AVX-NEXT: shrl $29, %ecx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: sarl $3, %ecx
; AVX-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
; AVX-NEXT: shrl $3, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: sarl $31, %ecx
; AVX-NEXT: shrl $28, %ecx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: sarl $4, %ecx
; AVX-NEXT: vpinsrd $3, %ecx, %xmm1, %xmm0
; AVX-NEXT: shrl $4, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
; AVX-NEXT: retq
%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
%2 = sdiv <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>