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https://github.com/RPCS3/llvm-mirror.git
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Use early exit and reduce indentation.
llvm-svn: 80631
This commit is contained in:
Bob Wilson
parent
0b8a1e2f69
commit
afc5184593
@ -791,132 +791,98 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() &&
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mi->getOperand(si).isUse() && "two address instruction invalid");
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// If the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
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// Rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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unsigned regASubIdx = mi->getOperand(ti).getSubReg();
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// If the two operands are the same, nothing needs to be done.
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if (mi->getOperand(ti).getReg() == mi->getOperand(si).getReg())
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continue;
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assert(TargetRegisterInfo::isVirtualRegister(regB) &&
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"cannot make instruction into two-address form");
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// Rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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unsigned regASubIdx = mi->getOperand(ti).getSubReg();
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assert(TargetRegisterInfo::isVirtualRegister(regB) &&
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"cannot make instruction into two-address form");
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#ifndef NDEBUG
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// First, verify that we don't have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert(i == ti ||
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!mi->getOperand(i).isReg() ||
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mi->getOperand(i).getReg() != regA);
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// First, verify that we don't have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert(i == ti ||
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!mi->getOperand(i).isReg() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!isKilled(*mi, regB, MRI, TII)) {
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// If regA is dead and the instruction can be deleted, just delete
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// it so it doesn't clobber regB.
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SmallVector<unsigned, 4> Kills;
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if (mi->getOperand(ti).isDead() &&
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isSafeToDelete(mi, regB, TII, Kills)) {
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SmallVector<std::pair<std::pair<unsigned, bool>
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,MachineInstr*>, 4> NewKills;
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bool ReallySafe = true;
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// If this instruction kills some virtual registers, we need
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// update the kill information. If it's not possible to do so,
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// then bail out.
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while (!Kills.empty()) {
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unsigned Kill = Kills.back();
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Kills.pop_back();
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if (TargetRegisterInfo::isPhysicalRegister(Kill)) {
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ReallySafe = false;
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break;
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}
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MachineInstr *LastKill = FindLastUseInMBB(Kill, &*mbbi, Dist);
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if (LastKill) {
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bool isModRef = LastKill->modifiesRegister(Kill);
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NewKills.push_back(std::make_pair(std::make_pair(Kill,isModRef),
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LastKill));
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} else {
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ReallySafe = false;
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break;
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}
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!isKilled(*mi, regB, MRI, TII)) {
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// If regA is dead and the instruction can be deleted, just delete
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// it so it doesn't clobber regB.
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SmallVector<unsigned, 4> Kills;
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if (mi->getOperand(ti).isDead() &&
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isSafeToDelete(mi, regB, TII, Kills)) {
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SmallVector<std::pair<std::pair<unsigned, bool>
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,MachineInstr*>, 4> NewKills;
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bool ReallySafe = true;
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// If this instruction kills some virtual registers, we need
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// update the kill information. If it's not possible to do so,
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// then bail out.
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while (!Kills.empty()) {
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unsigned Kill = Kills.back();
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Kills.pop_back();
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if (TargetRegisterInfo::isPhysicalRegister(Kill)) {
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ReallySafe = false;
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break;
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}
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MachineInstr *LastKill = FindLastUseInMBB(Kill, &*mbbi, Dist);
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if (LastKill) {
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bool isModRef = LastKill->modifiesRegister(Kill);
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NewKills.push_back(std::make_pair(std::make_pair(Kill,isModRef),
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LastKill));
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} else {
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ReallySafe = false;
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break;
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}
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}
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if (ReallySafe) {
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if (LV) {
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while (!NewKills.empty()) {
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MachineInstr *NewKill = NewKills.back().second;
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unsigned Kill = NewKills.back().first.first;
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bool isDead = NewKills.back().first.second;
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NewKills.pop_back();
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if (LV->removeVirtualRegisterKilled(Kill, mi)) {
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if (isDead)
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LV->addVirtualRegisterDead(Kill, NewKill);
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else
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LV->addVirtualRegisterKilled(Kill, NewKill);
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}
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if (ReallySafe) {
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if (LV) {
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while (!NewKills.empty()) {
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MachineInstr *NewKill = NewKills.back().second;
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unsigned Kill = NewKills.back().first.first;
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bool isDead = NewKills.back().first.second;
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NewKills.pop_back();
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if (LV->removeVirtualRegisterKilled(Kill, mi)) {
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if (isDead)
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LV->addVirtualRegisterDead(Kill, NewKill);
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else
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LV->addVirtualRegisterKilled(Kill, NewKill);
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}
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}
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// We're really going to nuke the old inst. If regB was marked
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// as a kill we need to update its Kills list.
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if (mi->getOperand(si).isKill())
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LV->removeVirtualRegisterKilled(regB, mi);
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mbbi->erase(mi); // Nuke the old inst.
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mi = nmi;
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++NumDeletes;
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break; // Done with this instruction.
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}
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}
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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unsigned SrcOp1, SrcOp2;
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if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
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TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
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unsigned regC = 0;
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if (si == SrcOp1)
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regC = mi->getOperand(SrcOp2).getReg();
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else if (si == SrcOp2)
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regC = mi->getOperand(SrcOp1).getReg();
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if (isKilled(*mi, regC, MRI, TII)) {
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if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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}
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// We're really going to nuke the old inst. If regB was marked
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// as a kill we need to update its Kills list.
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if (mi->getOperand(si).isKill())
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LV->removeVirtualRegisterKilled(regB, mi);
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.isConvertibleTo3Addr()) {
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// FIXME: This assumes there are no more operands which are tied
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// to another register.
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#ifndef NDEBUG
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for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
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assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
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#endif
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if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
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++NumConvertedTo3Addr;
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break; // Done with this instruction.
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}
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mbbi->erase(mi); // Nuke the old inst.
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mi = nmi;
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++NumDeletes;
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break; // Done with this instruction.
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}
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}
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// If it's profitable to commute the instruction, do so.
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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unsigned SrcOp1, SrcOp2;
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if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
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TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
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@ -925,73 +891,107 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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regC = mi->getOperand(SrcOp2).getReg();
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else if (si == SrcOp2)
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regC = mi->getOperand(SrcOp1).getReg();
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if (regC && isProfitableToCommute(regB, regC, mi, mbbi, Dist))
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if (isKilled(*mi, regC, MRI, TII)) {
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if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
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++NumAggrCommuted;
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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}
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// If it's profitable to convert the 2-address instruction to a
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// 3-address one, do so.
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if (TID.isConvertibleTo3Addr() && isProfitableToConv3Addr(regA)) {
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.isConvertibleTo3Addr()) {
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// FIXME: This assumes there are no more operands which are tied
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// to another register.
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#ifndef NDEBUG
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for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i)
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assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
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#endif
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if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
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++NumConvertedTo3Addr;
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break; // Done with this instruction.
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MRI->getRegClass(regB);
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MachineInstr *DefMI = MRI->getVRegDef(regB);
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// If it's safe and profitable, remat the definition instead of
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// copying it.
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if (DefMI &&
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DefMI->getDesc().isAsCheapAsAMove() &&
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DefMI->isSafeToReMat(TII, regB) &&
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isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
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DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
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TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
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ReMatRegs.set(regB);
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++NumReMats;
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} else {
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bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
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(void)Emitted;
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assert(Emitted && "Unable to issue a copy instruction!\n");
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}
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MachineBasicBlock::iterator prevMI = prior(mi);
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// Update DistanceMap.
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DistanceMap.insert(std::make_pair(prevMI, Dist));
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DistanceMap[mi] = ++Dist;
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// Update live variables for regB.
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if (LV) {
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if (LV->removeVirtualRegisterKilled(regB, mi))
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LV->addVirtualRegisterKilled(regB, prevMI);
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if (LV->removeVirtualRegisterDead(regB, mi))
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LV->addVirtualRegisterDead(regB, prevMI);
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}
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DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
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// Replace all occurences of regB with regA.
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isReg() &&
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mi->getOperand(i).getReg() == regB)
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mi->getOperand(i).setReg(regA);
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}
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assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
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mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
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MadeChange = true;
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DEBUG(errs() << "\t\trewrite to:\t" << *mi);
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}
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// If it's profitable to commute the instruction, do so.
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unsigned SrcOp1, SrcOp2;
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if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
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TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
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unsigned regC = 0;
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if (si == SrcOp1)
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regC = mi->getOperand(SrcOp2).getReg();
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else if (si == SrcOp2)
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regC = mi->getOperand(SrcOp1).getReg();
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if (regC && isProfitableToCommute(regB, regC, mi, mbbi, Dist))
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if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
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++NumAggrCommuted;
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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// If it's profitable to convert the 2-address instruction to a
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// 3-address one, do so.
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if (TID.isConvertibleTo3Addr() && isProfitableToConv3Addr(regA)) {
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if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
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++NumConvertedTo3Addr;
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break; // Done with this instruction.
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MRI->getRegClass(regB);
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MachineInstr *DefMI = MRI->getVRegDef(regB);
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// If it's safe and profitable, remat the definition instead of
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// copying it.
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if (DefMI &&
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DefMI->getDesc().isAsCheapAsAMove() &&
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DefMI->isSafeToReMat(TII, regB) &&
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isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
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DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
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TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
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ReMatRegs.set(regB);
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++NumReMats;
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} else {
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bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
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(void)Emitted;
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assert(Emitted && "Unable to issue a copy instruction!\n");
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}
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MachineBasicBlock::iterator prevMI = prior(mi);
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// Update DistanceMap.
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DistanceMap.insert(std::make_pair(prevMI, Dist));
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DistanceMap[mi] = ++Dist;
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// Update live variables for regB.
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if (LV) {
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if (LV->removeVirtualRegisterKilled(regB, mi))
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LV->addVirtualRegisterKilled(regB, prevMI);
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if (LV->removeVirtualRegisterDead(regB, mi))
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LV->addVirtualRegisterDead(regB, prevMI);
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}
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DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
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// Replace all occurences of regB with regA.
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isReg() &&
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mi->getOperand(i).getReg() == regB)
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mi->getOperand(i).setReg(regA);
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}
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assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
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mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
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MadeChange = true;
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DEBUG(errs() << "\t\trewrite to:\t" << *mi);
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}
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mi = nmi;
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