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https://github.com/RPCS3/llvm-mirror.git
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[LoopVectorize] Fix strict reductions where VF = 1
Currently we will allow loops with a fixed width VF of 1 to vectorize if the -enable-strict-reductions flag is set. However, the loop vectorizer will not use ordered reductions if `VF.isScalar()` and the resulting vectorized loop will be out of order. This patch removes `VF.isVector()` when checking if ordered reductions should be used. Also, instead of converting the FAdds to reductions if the VF = 1, operands of the FAdds are changed such that the order is preserved. Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D104533
This commit is contained in:
Kerry McLaughlin
parent
e51ded8676
commit
b00f0df573
@ -356,7 +356,8 @@ private:
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/// reductions, with one operand being vector and the other being the scalar
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/// reduction chain.
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void adjustRecipesForInLoopReductions(VPlanPtr &Plan,
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VPRecipeBuilder &RecipeBuilder);
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VPRecipeBuilder &RecipeBuilder,
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ElementCount MinVF);
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};
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} // namespace llvm
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@ -4344,8 +4344,7 @@ void InnerLoopVectorizer::fixReduction(VPWidenPHIRecipe *PhiR,
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// any loop invariant values.
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BasicBlock *VectorLoopLatch = LI->getLoopFor(LoopVectorBody)->getLoopLatch();
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bool IsOrdered = State.VF.isVector() && IsInLoopReductionPhi &&
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Cost->useOrderedReductions(RdxDesc);
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bool IsOrdered = IsInLoopReductionPhi && Cost->useOrderedReductions(RdxDesc);
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for (unsigned Part = 0; Part < UF; ++Part) {
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if (IsOrdered && Part > 0)
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@ -4759,8 +4758,7 @@ void InnerLoopVectorizer::widenPHIInstruction(Instruction *PN,
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Type *VecTy =
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ScalarPHI ? PN->getType() : VectorType::get(PN->getType(), State.VF);
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bool IsOrdered = State.VF.isVector() &&
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Cost->isInLoopReduction(cast<PHINode>(PN)) &&
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bool IsOrdered = Cost->isInLoopReduction(cast<PHINode>(PN)) &&
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Cost->useOrderedReductions(*RdxDesc);
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unsigned LastPartForNewPhi = IsOrdered ? 1 : State.UF;
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for (unsigned Part = 0; Part < LastPartForNewPhi; ++Part) {
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@ -9280,8 +9278,7 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes(
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}
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// Adjust the recipes for any inloop reductions.
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if (Range.Start.isVector())
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adjustRecipesForInLoopReductions(Plan, RecipeBuilder);
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adjustRecipesForInLoopReductions(Plan, RecipeBuilder, Range.Start);
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// Finally, if tail is folded by masking, introduce selects between the phi
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// and the live-out instruction of each reduction, at the end of the latch.
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@ -9356,12 +9353,15 @@ VPlanPtr LoopVectorizationPlanner::buildVPlan(VFRange &Range) {
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// reductions, with one operand being vector and the other being the scalar
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// reduction chain.
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void LoopVectorizationPlanner::adjustRecipesForInLoopReductions(
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VPlanPtr &Plan, VPRecipeBuilder &RecipeBuilder) {
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VPlanPtr &Plan, VPRecipeBuilder &RecipeBuilder, ElementCount MinVF) {
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for (auto &Reduction : CM.getInLoopReductionChains()) {
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PHINode *Phi = Reduction.first;
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RecurrenceDescriptor &RdxDesc = Legal->getReductionVars()[Phi];
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const SmallVector<Instruction *, 4> &ReductionOperations = Reduction.second;
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if (MinVF.isScalar() && !CM.useOrderedReductions(RdxDesc))
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continue;
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// ReductionOperations are orders top-down from the phi's use to the
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// LoopExitValue. We keep a track of the previous item (the Chain) to tell
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// which of the two operands will remain scalar and which will be reduced.
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@ -9378,7 +9378,7 @@ void LoopVectorizationPlanner::adjustRecipesForInLoopReductions(
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"Expected to replace a VPWidenSelectSC");
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FirstOpId = 1;
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} else {
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assert(isa<VPWidenRecipe>(WidenRecipe) &&
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assert((MinVF.isScalar() || isa<VPWidenRecipe>(WidenRecipe)) &&
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"Expected to replace a VPWidenSC");
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FirstOpId = 0;
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}
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@ -9527,8 +9527,13 @@ void VPReductionRecipe::execute(VPTransformState &State) {
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Value *NewRed;
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Value *NextInChain;
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if (IsOrdered) {
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NewRed = createOrderedReduction(State.Builder, *RdxDesc, NewVecOp,
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PrevInChain);
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if (State.VF.isVector())
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NewRed = createOrderedReduction(State.Builder, *RdxDesc, NewVecOp,
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PrevInChain);
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else
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NewRed = State.Builder.CreateBinOp(
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(Instruction::BinaryOps)getUnderlyingInstr()->getOpcode(),
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PrevInChain, NewVecOp);
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PrevInChain = NewRed;
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} else {
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PrevInChain = State.get(getChainOp(), Part);
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@ -693,14 +693,89 @@ for.end:
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ret float %add6
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}
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!0 = distinct !{!0, !4, !7, !9}
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!1 = distinct !{!1, !4, !8, !9}
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!2 = distinct !{!2, !5, !7, !9}
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!3 = distinct !{!3, !6, !7, !9, !10}
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!4 = !{!"llvm.loop.vectorize.width", i32 8}
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!5 = !{!"llvm.loop.vectorize.width", i32 4}
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!6 = !{!"llvm.loop.vectorize.width", i32 2}
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!7 = !{!"llvm.loop.interleave.count", i32 1}
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!8 = !{!"llvm.loop.interleave.count", i32 4}
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!9 = !{!"llvm.loop.vectorize.enable", i1 true}
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!10 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
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; Test reductions for a VF of 1 and a UF > 1.
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define float @fadd_scalar_vf(float* noalias nocapture readonly %a, i64 %n) {
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; CHECK-ORDERED-LABEL: @fadd_scalar_vf
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; CHECK-ORDERED: vector.body
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; CHECK-ORDERED: %[[VEC_PHI:.*]] = phi float [ 0.000000e+00, {{.*}} ], [ %[[FADD4:.*]], %vector.body ]
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; CHECK-ORDERED: %[[LOAD1:.*]] = load float, float*
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; CHECK-ORDERED: %[[LOAD2:.*]] = load float, float*
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; CHECK-ORDERED: %[[LOAD3:.*]] = load float, float*
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; CHECK-ORDERED: %[[LOAD4:.*]] = load float, float*
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; CHECK-ORDERED: %[[FADD1:.*]] = fadd float %[[VEC_PHI]], %[[LOAD1]]
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; CHECK-ORDERED: %[[FADD2:.*]] = fadd float %[[FADD1]], %[[LOAD2]]
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; CHECK-ORDERED: %[[FADD3:.*]] = fadd float %[[FADD2]], %[[LOAD3]]
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; CHECK-ORDERED: %[[FADD4]] = fadd float %[[FADD3]], %[[LOAD4]]
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; CHECK-ORDERED-NOT: call float @llvm.vector.reduce.fadd
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; CHECK-ORDERED: scalar.ph
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; CHECK-ORDERED: %[[MERGE_RDX:.*]] = phi float [ 0.000000e+00, %entry ], [ %[[FADD4]], %middle.block ]
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; CHECK-ORDERED: for.body
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; CHECK-ORDERED: %[[SUM_PHI:.*]] = phi float [ %[[MERGE_RDX]], %scalar.ph ], [ %[[FADD5:.*]], %for.body ]
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; CHECK-ORDERED: %[[LOAD5:.*]] = load float, float*
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; CHECK-ORDERED: %[[FADD5]] = fadd float %[[LOAD5]], %[[SUM_PHI]]
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; CHECK-ORDERED: for.end
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; CHECK-ORDERED: %[[RES_PHI:.*]] = phi float [ %[[FADD5]], %for.body ], [ %[[FADD4]], %middle.block ]
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; CHECK-ORDERED: ret float %[[RES_PHI]]
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; CHECK-UNORDERED-LABEL: @fadd_scalar_vf
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; CHECK-UNORDERED: vector.body
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; CHECK-UNORDERED: %[[VEC_PHI1:.*]] = phi float [ 0.000000e+00, %vector.ph ], [ %[[FADD1:.*]], %vector.body ]
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; CHECK-UNORDERED: %[[VEC_PHI2:.*]] = phi float [ -0.000000e+00, %vector.ph ], [ %[[FADD2:.*]], %vector.body ]
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; CHECK-UNORDERED: %[[VEC_PHI3:.*]] = phi float [ -0.000000e+00, %vector.ph ], [ %[[FADD3:.*]], %vector.body ]
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; CHECK-UNORDERED: %[[VEC_PHI4:.*]] = phi float [ -0.000000e+00, %vector.ph ], [ %[[FADD4:.*]], %vector.body ]
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; CHECK-UNORDERED: %[[LOAD1:.*]] = load float, float*
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; CHECK-UNORDERED: %[[LOAD2:.*]] = load float, float*
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; CHECK-UNORDERED: %[[LOAD3:.*]] = load float, float*
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; CHECK-UNORDERED: %[[LOAD4:.*]] = load float, float*
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; CHECK-UNORDERED: %[[FADD1]] = fadd float %[[LOAD1]], %[[VEC_PHI1]]
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; CHECK-UNORDERED: %[[FADD2]] = fadd float %[[LOAD2]], %[[VEC_PHI2]]
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; CHECK-UNORDERED: %[[FADD3]] = fadd float %[[LOAD3]], %[[VEC_PHI3]]
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; CHECK-UNORDERED: %[[FADD4]] = fadd float %[[LOAD4]], %[[VEC_PHI4]]
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; CHECK-UNORDERED-NOT: call float @llvm.vector.reduce.fadd
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; CHECK-UNORDERED: middle.block
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; CHECK-UNORDERED: %[[BIN_RDX1:.*]] = fadd float %[[FADD2]], %[[FADD1]]
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; CHECK-UNORDERED: %[[BIN_RDX2:.*]] = fadd float %[[FADD3]], %[[BIN_RDX1]]
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; CHECK-UNORDERED: %[[BIN_RDX3:.*]] = fadd float %[[FADD4]], %[[BIN_RDX2]]
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; CHECK-UNORDERED: scalar.ph
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; CHECK-UNORDERED: %[[MERGE_RDX:.*]] = phi float [ 0.000000e+00, %entry ], [ %[[BIN_RDX3]], %middle.block ]
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; CHECK-UNORDERED: for.body
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; CHECK-UNORDERED: %[[SUM_PHI:.*]] = phi float [ %[[MERGE_RDX]], %scalar.ph ], [ %[[FADD5:.*]], %for.body ]
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; CHECK-UNORDERED: %[[LOAD5:.*]] = load float, float*
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; CHECK-UNORDERED: %[[FADD5]] = fadd float %[[LOAD5]], %[[SUM_PHI]]
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; CHECK-UNORDERED: for.end
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; CHECK-UNORDERED: %[[RES_PHI:.*]] = phi float [ %[[FADD5]], %for.body ], [ %[[BIN_RDX3]], %middle.block ]
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; CHECK-UNORDERED: ret float %[[RES_PHI]]
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; CHECK-NOT-VECTORIZED-LABEL: @fadd_scalar_vf
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; CHECK-NOT-VECTORIZED-NOT: @vector.body
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%sum.07 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
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%arrayidx = getelementptr inbounds float, float* %a, i64 %iv
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%0 = load float, float* %arrayidx, align 4
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%add = fadd float %0, %sum.07
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %n
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br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !4
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for.end:
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ret float %add
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}
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!0 = distinct !{!0, !5, !9, !11}
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!1 = distinct !{!1, !5, !10, !11}
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!2 = distinct !{!2, !6, !9, !11}
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!3 = distinct !{!3, !7, !9, !11, !12}
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!4 = distinct !{!4, !8, !10, !11}
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!5 = !{!"llvm.loop.vectorize.width", i32 8}
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!6 = !{!"llvm.loop.vectorize.width", i32 4}
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!7 = !{!"llvm.loop.vectorize.width", i32 2}
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!8 = !{!"llvm.loop.vectorize.width", i32 1}
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!9 = !{!"llvm.loop.interleave.count", i32 1}
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!10 = !{!"llvm.loop.interleave.count", i32 4}
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!11 = !{!"llvm.loop.vectorize.enable", i1 true}
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!12 = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
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