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Expand fabs / fneg to and / xor.

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llvm-svn: 32619
This commit is contained in:
Evan Cheng 2006-12-16 00:52:40 +00:00
parent fb82dcf9ee
commit b0292a750a
1 changed files with 22 additions and 3 deletions
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25
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -5055,9 +5055,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
case ISD::FNEG:
Lo = ExpandLibCall(((VT == MVT::f32) ? "__negsf2" : "__negdf2"), Node, Hi);
break;
case ISD::FADD:
Lo = ExpandLibCall(((VT == MVT::f32) ? "__addsf3" : "__adddf3"), Node, Hi);
break;
@ -5107,6 +5104,28 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
Lo = ExpandLibCall(FnName, Node, Hi);
break;
}
case ISD::FABS: {
SDOperand Mask = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
: DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
if (getTypeAction(NVT) == Expand)
ExpandOp(Lo, Lo, Hi);
break;
}
case ISD::FNEG: {
SDOperand Mask = (VT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
: DAG.getConstantFP(BitsToFloat(1U << 31), VT);
Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
if (getTypeAction(NVT) == Expand)
ExpandOp(Lo, Lo, Hi);
break;
}
}
// Make sure the resultant values have been legalized themselves, unless this