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https://github.com/RPCS3/llvm-mirror.git
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Eliminate the CurMBB member from SelectionDAGBuilder. For places that
need it, just pass around the parent block of the current instruction explicitly. llvm-svn: 101822
This commit is contained in:
parent
e52396cb52
commit
b02e2f6c92
@ -980,7 +980,8 @@ void
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SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB) {
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MachineBasicBlock *CurBB,
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MachineBasicBlock *SwitchBB) {
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const BasicBlock *BB = CurBB->getBasicBlock();
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// If the leaf of the tree is a comparison, merge the condition into
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@ -989,7 +990,7 @@ SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
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// The operands of the cmp have to be in this block. We don't know
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// how to export them from some other block. If this is the first block
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// of the sequence, no exporting is needed.
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if (CurBB == CurMBB ||
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if (CurBB == SwitchBB ||
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(isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
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isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
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ISD::CondCode Condition;
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@ -1020,6 +1021,7 @@ void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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MachineBasicBlock *CurBB,
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MachineBasicBlock *SwitchBB,
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unsigned Opc) {
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// If this node is not part of the or/and tree, emit it as a branch.
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const Instruction *BOp = dyn_cast<Instruction>(Cond);
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@ -1028,7 +1030,7 @@ void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
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BOp->getParent() != CurBB->getBasicBlock() ||
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!InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
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!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
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EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
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EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
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return;
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}
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@ -1048,10 +1050,10 @@ void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
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//
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// Emit the LHS condition.
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FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
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FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
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// Emit the RHS condition into TmpBB.
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FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
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FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
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} else {
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assert(Opc == Instruction::And && "Unknown merge op!");
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// Codegen X & Y as:
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@ -1064,10 +1066,10 @@ void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
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// This requires creation of TmpBB after CurBB.
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// Emit the LHS condition.
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FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
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FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
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// Emit the RHS condition into TmpBB.
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FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
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FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
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}
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}
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@ -1103,18 +1105,20 @@ SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
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}
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void SelectionDAGBuilder::visitBr(const BranchInst &I) {
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MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()];
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// Update machine-CFG edges.
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MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
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// Figure out which block is immediately after the current one.
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MachineBasicBlock *NextBlock = 0;
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MachineFunction::iterator BBI = CurMBB;
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MachineFunction::iterator BBI = BrMBB;
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if (++BBI != FuncInfo.MF->end())
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NextBlock = BBI;
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if (I.isUnconditional()) {
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// Update machine-CFG edges.
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CurMBB->addSuccessor(Succ0MBB);
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BrMBB->addSuccessor(Succ0MBB);
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// If this is not a fall-through branch, emit the branch.
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if (Succ0MBB != NextBlock)
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@ -1149,11 +1153,12 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
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if (BOp->hasOneUse() &&
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(BOp->getOpcode() == Instruction::And ||
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BOp->getOpcode() == Instruction::Or)) {
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FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
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FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
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BOp->getOpcode());
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// If the compares in later blocks need to use values not currently
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// exported from this block, export them now. This block should always
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// be the first entry.
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assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
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assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
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// Allow some cases to be rejected.
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if (ShouldEmitAsBranches(SwitchCases)) {
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@ -1163,7 +1168,7 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
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}
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// Emit the branch for this block.
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visitSwitchCase(SwitchCases[0]);
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visitSwitchCase(SwitchCases[0], BrMBB);
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SwitchCases.erase(SwitchCases.begin());
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return;
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}
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@ -1179,16 +1184,17 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
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// Create a CaseBlock record representing this branch.
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CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
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NULL, Succ0MBB, Succ1MBB, CurMBB);
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NULL, Succ0MBB, Succ1MBB, BrMBB);
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// Use visitSwitchCase to actually insert the fast branch sequence for this
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// cond branch.
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visitSwitchCase(CB);
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visitSwitchCase(CB, BrMBB);
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}
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/// visitSwitchCase - Emits the necessary code to represent a single node in
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/// the binary search tree resulting from lowering a switch instruction.
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void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
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void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
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MachineBasicBlock *SwitchBB) {
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SDValue Cond;
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SDValue CondLHS = getValue(CB.CmpLHS);
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DebugLoc dl = getCurDebugLoc();
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@ -1227,13 +1233,13 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
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}
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// Update successor info
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CurMBB->addSuccessor(CB.TrueBB);
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CurMBB->addSuccessor(CB.FalseBB);
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SwitchBB->addSuccessor(CB.TrueBB);
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SwitchBB->addSuccessor(CB.FalseBB);
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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MachineBasicBlock *NextBlock = 0;
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MachineFunction::iterator BBI = CurMBB;
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MachineFunction::iterator BBI = SwitchBB;
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if (++BBI != FuncInfo.MF->end())
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NextBlock = BBI;
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@ -1251,11 +1257,11 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
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// If the branch was constant folded, fix up the CFG.
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if (BrCond.getOpcode() == ISD::BR) {
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CurMBB->removeSuccessor(CB.FalseBB);
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SwitchBB->removeSuccessor(CB.FalseBB);
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} else {
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// Otherwise, go ahead and insert the false branch.
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if (BrCond == getControlRoot())
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CurMBB->removeSuccessor(CB.TrueBB);
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SwitchBB->removeSuccessor(CB.TrueBB);
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if (CB.FalseBB != NextBlock)
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BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
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@ -1282,7 +1288,8 @@ void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
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/// visitJumpTableHeader - This function emits necessary code to produce index
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/// in the JumpTable from switch case.
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void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
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JumpTableHeader &JTH) {
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JumpTableHeader &JTH,
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MachineBasicBlock *SwitchBB) {
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// Subtract the lowest switch case value from the value being switched on and
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// conditional branch to default mbb if the result is greater than the
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// difference between smallest and largest cases.
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@ -1314,7 +1321,7 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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MachineBasicBlock *NextBlock = 0;
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MachineFunction::iterator BBI = CurMBB;
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MachineFunction::iterator BBI = SwitchBB;
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if (++BBI != FuncInfo.MF->end())
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NextBlock = BBI;
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@ -1332,7 +1339,8 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
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/// visitBitTestHeader - This function emits necessary code to produce value
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/// suitable for "bit tests"
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void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
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void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
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MachineBasicBlock *SwitchBB) {
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// Subtract the minimum value
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SDValue SwitchOp = getValue(B.SValue);
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EVT VT = SwitchOp.getValueType();
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@ -1355,14 +1363,14 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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MachineBasicBlock *NextBlock = 0;
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MachineFunction::iterator BBI = CurMBB;
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MachineFunction::iterator BBI = SwitchBB;
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if (++BBI != FuncInfo.MF->end())
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NextBlock = BBI;
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MachineBasicBlock* MBB = B.Cases[0].ThisBB;
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CurMBB->addSuccessor(B.Default);
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CurMBB->addSuccessor(MBB);
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SwitchBB->addSuccessor(B.Default);
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SwitchBB->addSuccessor(MBB);
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SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
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MVT::Other, CopyTo, RangeCmp,
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@ -1378,7 +1386,8 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
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/// visitBitTestCase - this function produces one "bit test"
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void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
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unsigned Reg,
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BitTestCase &B) {
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BitTestCase &B,
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MachineBasicBlock *SwitchBB) {
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// Make desired shift
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SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
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TLI.getPointerTy());
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@ -1396,8 +1405,8 @@ void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
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AndOp, DAG.getConstant(0, TLI.getPointerTy()),
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ISD::SETNE);
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CurMBB->addSuccessor(B.TargetBB);
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CurMBB->addSuccessor(NextMBB);
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SwitchBB->addSuccessor(B.TargetBB);
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SwitchBB->addSuccessor(NextMBB);
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SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
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MVT::Other, getControlRoot(),
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@ -1406,7 +1415,7 @@ void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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MachineBasicBlock *NextBlock = 0;
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MachineFunction::iterator BBI = CurMBB;
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MachineFunction::iterator BBI = SwitchBB;
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if (++BBI != FuncInfo.MF->end())
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NextBlock = BBI;
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@ -1418,6 +1427,8 @@ void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
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}
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void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
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MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()];
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// Retrieve successors.
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MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
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MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
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@ -1433,8 +1444,8 @@ void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
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CopyToExportRegsIfNeeded(&I);
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// Update successor info
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CurMBB->addSuccessor(Return);
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CurMBB->addSuccessor(LandingPad);
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InvokeMBB->addSuccessor(Return);
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InvokeMBB->addSuccessor(LandingPad);
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// Drop into normal successor.
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DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
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@ -1450,7 +1461,8 @@ void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
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bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default) {
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MachineBasicBlock *Default,
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MachineBasicBlock *SwitchBB) {
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Case& BackCase = *(CR.Range.second-1);
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// Size is the number of Cases represented by this range.
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@ -1519,8 +1531,8 @@ bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
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// code into the current block. Otherwise, push the CaseBlock onto the
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// vector to be later processed by SDISel, and insert the node's MBB
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// before the next MBB.
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if (CurBlock == CurMBB)
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visitSwitchCase(CB);
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if (CurBlock == SwitchBB)
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visitSwitchCase(CB, SwitchBB);
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else
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SwitchCases.push_back(CB);
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@ -1547,7 +1559,8 @@ static APInt ComputeRange(const APInt &First, const APInt &Last) {
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bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default) {
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB) {
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Case& FrontCase = *CR.Range.first;
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Case& BackCase = *(CR.Range.second-1);
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@ -1628,9 +1641,9 @@ bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
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// Set the jump table information so that we can codegen it as a second
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// MachineBasicBlock
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JumpTable JT(-1U, JTI, JumpTableBB, Default);
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JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
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if (CR.CaseBB == CurMBB)
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visitJumpTableHeader(JT, JTH);
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JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
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if (CR.CaseBB == SwitchBB)
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visitJumpTableHeader(JT, JTH, SwitchBB);
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JTCases.push_back(JumpTableBlock(JTH, JT));
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@ -1642,7 +1655,8 @@ bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
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bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default) {
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MachineBasicBlock *Default,
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MachineBasicBlock *SwitchBB) {
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// Get the MachineFunction which holds the current MBB. This is used when
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// inserting any additional MBBs necessary to represent the switch.
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MachineFunction *CurMF = FuncInfo.MF;
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@ -1756,8 +1770,8 @@ bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
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// Otherwise, branch to LHS.
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CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
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if (CR.CaseBB == CurMBB)
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visitSwitchCase(CB);
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if (CR.CaseBB == SwitchBB)
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visitSwitchCase(CB, SwitchBB);
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else
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SwitchCases.push_back(CB);
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@ -1770,7 +1784,8 @@ bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
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bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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const Value* SV,
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MachineBasicBlock* Default){
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MachineBasicBlock* Default,
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MachineBasicBlock *SwitchBB){
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EVT PTy = TLI.getPointerTy();
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unsigned IntPtrBits = PTy.getSizeInBits();
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@ -1885,11 +1900,11 @@ bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
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}
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BitTestBlock BTB(lowBound, cmpRange, SV,
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-1U, (CR.CaseBB == CurMBB),
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-1U, (CR.CaseBB == SwitchBB),
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CR.CaseBB, Default, BTC);
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if (CR.CaseBB == CurMBB)
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visitBitTestHeader(BTB);
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if (CR.CaseBB == SwitchBB)
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visitBitTestHeader(BTB, SwitchBB);
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BitTestCases.push_back(BTB);
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@ -1940,6 +1955,8 @@ size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
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}
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void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
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MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()];
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// Figure out which block is immediately after the current one.
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MachineBasicBlock *NextBlock = 0;
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MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
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@ -1950,7 +1967,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
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// Update machine-CFG edges.
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// If this is not a fall-through branch, emit the branch.
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CurMBB->addSuccessor(Default);
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SwitchMBB->addSuccessor(Default);
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if (Default != NextBlock)
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DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
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MVT::Other, getControlRoot(),
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@ -1975,34 +1992,37 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
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// Push the initial CaseRec onto the worklist
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CaseRecVector WorkList;
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WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
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WorkList.push_back(CaseRec(SwitchMBB,0,0,
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CaseRange(Cases.begin(),Cases.end())));
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while (!WorkList.empty()) {
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// Grab a record representing a case range to process off the worklist
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CaseRec CR = WorkList.back();
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WorkList.pop_back();
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if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
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if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
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continue;
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// If the range has few cases (two or less) emit a series of specific
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// tests.
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if (handleSmallSwitchRange(CR, WorkList, SV, Default))
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if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
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continue;
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// If the switch has more than 5 blocks, and at least 40% dense, and the
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// target supports indirect branches, then emit a jump table rather than
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// lowering the switch to a binary tree of conditional branches.
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if (handleJTSwitchCase(CR, WorkList, SV, Default))
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if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
|
||||
continue;
|
||||
|
||||
// Emit binary tree. We need to pick a pivot, and push left and right ranges
|
||||
// onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
|
||||
handleBTSplitSwitchCase(CR, WorkList, SV, Default);
|
||||
handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
|
||||
}
|
||||
}
|
||||
|
||||
void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
|
||||
MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()];
|
||||
|
||||
// Update machine-CFG edges with unique successors.
|
||||
SmallVector<BasicBlock*, 32> succs;
|
||||
succs.reserve(I.getNumSuccessors());
|
||||
@ -2011,7 +2031,7 @@ void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
|
||||
array_pod_sort(succs.begin(), succs.end());
|
||||
succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
|
||||
for (unsigned i = 0, e = succs.size(); i != e; ++i)
|
||||
CurMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
|
||||
IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
|
||||
|
||||
DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
|
||||
MVT::Other, getControlRoot(),
|
||||
@ -3819,7 +3839,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
||||
}
|
||||
case Intrinsic::eh_exception: {
|
||||
// Insert the EXCEPTIONADDR instruction.
|
||||
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
|
||||
assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
|
||||
"Call to eh.exception not in landing pad!");
|
||||
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
|
||||
SDValue Ops[1];
|
||||
Ops[0] = DAG.getRoot();
|
||||
@ -3830,16 +3851,17 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
|
||||
}
|
||||
|
||||
case Intrinsic::eh_selector: {
|
||||
MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()];
|
||||
MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
|
||||
if (CurMBB->isLandingPad())
|
||||
AddCatchInfo(I, &MMI, CurMBB);
|
||||
if (CallMBB->isLandingPad())
|
||||
AddCatchInfo(I, &MMI, CallMBB);
|
||||
else {
|
||||
#ifndef NDEBUG
|
||||
FuncInfo.CatchInfoLost.insert(&I);
|
||||
#endif
|
||||
// FIXME: Mark exception selector register as live in. Hack for PR1508.
|
||||
unsigned Reg = TLI.getExceptionSelectorRegister();
|
||||
if (Reg) CurMBB->addLiveIn(Reg);
|
||||
if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg);
|
||||
}
|
||||
|
||||
// Insert the EHSELECTION instruction.
|
||||
@ -5340,7 +5362,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
|
||||
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
|
||||
if (OpInfo.isIndirect) {
|
||||
// This happens on gcc/testsuite/gcc.dg/pr8788-1.c
|
||||
LLVMContext &Ctx = CurMBB->getParent()->getFunction()->getContext();
|
||||
LLVMContext &Ctx = *DAG.getContext();
|
||||
Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
|
||||
" don't know how to handle tied "
|
||||
"indirect register inputs");
|
||||
|
@ -82,8 +82,6 @@ class ZExtInst;
|
||||
/// implementation that is parameterized by a TargetLowering object.
|
||||
///
|
||||
class SelectionDAGBuilder {
|
||||
MachineBasicBlock *CurMBB;
|
||||
|
||||
/// CurDebugLoc - current file + line number. Changes as we build the DAG.
|
||||
DebugLoc CurDebugLoc;
|
||||
|
||||
@ -350,8 +348,6 @@ public:
|
||||
|
||||
void visit(unsigned Opcode, const User &I);
|
||||
|
||||
void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
|
||||
|
||||
SDValue getValue(const Value *V);
|
||||
|
||||
void setValue(const Value *V, SDValue NewN) {
|
||||
@ -366,10 +362,11 @@ public:
|
||||
|
||||
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
||||
unsigned Opc);
|
||||
MachineBasicBlock *SwitchBB, unsigned Opc);
|
||||
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
MachineBasicBlock *CurBB);
|
||||
MachineBasicBlock *CurBB,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
|
||||
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
|
||||
void CopyToExportRegsIfNeeded(const Value *V);
|
||||
@ -389,27 +386,34 @@ private:
|
||||
bool handleSmallSwitchRange(CaseRec& CR,
|
||||
CaseRecVector& WorkList,
|
||||
const Value* SV,
|
||||
MachineBasicBlock* Default);
|
||||
MachineBasicBlock* Default,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
bool handleJTSwitchCase(CaseRec& CR,
|
||||
CaseRecVector& WorkList,
|
||||
const Value* SV,
|
||||
MachineBasicBlock* Default);
|
||||
MachineBasicBlock* Default,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
bool handleBTSplitSwitchCase(CaseRec& CR,
|
||||
CaseRecVector& WorkList,
|
||||
const Value* SV,
|
||||
MachineBasicBlock* Default);
|
||||
MachineBasicBlock* Default,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
bool handleBitTestsSwitchCase(CaseRec& CR,
|
||||
CaseRecVector& WorkList,
|
||||
const Value* SV,
|
||||
MachineBasicBlock* Default);
|
||||
MachineBasicBlock* Default,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
public:
|
||||
void visitSwitchCase(CaseBlock &CB);
|
||||
void visitBitTestHeader(BitTestBlock &B);
|
||||
void visitSwitchCase(CaseBlock &CB,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
|
||||
void visitBitTestCase(MachineBasicBlock* NextMBB,
|
||||
unsigned Reg,
|
||||
BitTestCase &B);
|
||||
BitTestCase &B,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
void visitJumpTable(JumpTable &JT);
|
||||
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
|
||||
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
|
||||
MachineBasicBlock *SwitchBB);
|
||||
|
||||
private:
|
||||
// These all get lowered before this pass.
|
||||
|
@ -253,8 +253,6 @@ void SelectionDAGISel::SelectBasicBlock(const BasicBlock *LLVMBB,
|
||||
BasicBlock::const_iterator Begin,
|
||||
BasicBlock::const_iterator End,
|
||||
bool &HadTailCall) {
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
|
||||
// Lower all of the non-terminator instructions. If a call is emitted
|
||||
// as a tail call, cease emitting nodes for this block. Terminators
|
||||
// are handled below.
|
||||
@ -922,9 +920,8 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
if (!SDB->BitTestCases[i].Emitted) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDB->BitTestCases[i].Parent;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
SDB->visitBitTestHeader(SDB->BitTestCases[i]);
|
||||
SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDB->clear();
|
||||
@ -933,16 +930,17 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDB->BitTestCases[i].Cases[j].ThisBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
if (j+1 != ej)
|
||||
SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
|
||||
SDB->BitTestCases[i].Reg,
|
||||
SDB->BitTestCases[i].Cases[j]);
|
||||
SDB->BitTestCases[i].Cases[j],
|
||||
BB);
|
||||
else
|
||||
SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
|
||||
SDB->BitTestCases[i].Reg,
|
||||
SDB->BitTestCases[i].Cases[j]);
|
||||
SDB->BitTestCases[i].Cases[j],
|
||||
BB);
|
||||
|
||||
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
@ -989,9 +987,9 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
if (!SDB->JTCases[i].first.Emitted) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDB->JTCases[i].first.HeaderBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
|
||||
SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
|
||||
BB);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
SDB->clear();
|
||||
@ -999,7 +997,6 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
BB = SDB->JTCases[i].second.MBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
// Emit the code
|
||||
SDB->visitJumpTable(SDB->JTCases[i].second);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
@ -1047,10 +1044,9 @@ SelectionDAGISel::FinishBasicBlock() {
|
||||
for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
|
||||
// Set the current basic block to the mbb we wish to insert the code into
|
||||
MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
|
||||
SDB->setCurrentBasicBlock(BB);
|
||||
|
||||
// Emit the code
|
||||
SDB->visitSwitchCase(SDB->SwitchCases[i]);
|
||||
SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
|
||||
CurDAG->setRoot(SDB->getRoot());
|
||||
CodeGenAndEmitDAG();
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user