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[AArch64][SVE] Add support for DestructiveBinaryImm DestructiveInstType
Support prefixing destructive operations, with the MOVPRFX instruction, to build constructive operations. Differential Revision: https://reviews.llvm.org/D75064
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@ -412,6 +412,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
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}
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}
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LLVM_FALLTHROUGH;
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LLVM_FALLTHROUGH;
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case AArch64::DestructiveBinary:
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case AArch64::DestructiveBinary:
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case AArch64::DestructiveBinaryImm:
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std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3);
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std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3);
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break;
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break;
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default:
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default:
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@ -430,6 +431,9 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
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DstReg != MI.getOperand(DOPIdx).getReg() ||
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DstReg != MI.getOperand(DOPIdx).getReg() ||
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MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg();
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MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg();
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break;
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break;
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case AArch64::DestructiveBinaryImm:
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DOPRegIsUnique = true;
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break;
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}
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}
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assert (DOPRegIsUnique && "The destructive operand should be unique");
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assert (DOPRegIsUnique && "The destructive operand should be unique");
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@ -498,6 +502,7 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
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switch (DType) {
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switch (DType) {
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case AArch64::DestructiveBinaryImm:
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case AArch64::DestructiveBinaryComm:
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case AArch64::DestructiveBinaryComm:
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case AArch64::DestructiveBinaryCommWithRev:
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case AArch64::DestructiveBinaryCommWithRev:
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DOP.add(MI.getOperand(PredIdx))
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DOP.add(MI.getOperand(PredIdx))
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@ -1131,17 +1131,22 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
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defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">;
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defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">;
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// Predicated shifts
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// Predicated shifts
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defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">;
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defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr", "ASR_ZPZI">;
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defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">;
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defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr", "LSR_ZPZI">;
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defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">;
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defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">;
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defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd", int_aarch64_sve_asrd>;
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defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd", "ASRD_ZPZI", int_aarch64_sve_asrd>;
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defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr", int_aarch64_sve_asr>;
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defm ASR_ZPZZ : sve_int_bin_pred_zx<int_aarch64_sve_asr>;
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defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr", int_aarch64_sve_lsr>;
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defm LSR_ZPZZ : sve_int_bin_pred_zx<int_aarch64_sve_lsr>;
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defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl", int_aarch64_sve_lsl>;
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defm LSL_ZPZZ : sve_int_bin_pred_zx<int_aarch64_sve_lsl>;
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defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr", null_frag>;
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defm ASRD_ZPZI : sve_int_bin_pred_shift_0_right_zx<int_aarch64_sve_asrd>;
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defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr", null_frag>;
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defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr", null_frag>;
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defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr", "ASR_ZPZZ", int_aarch64_sve_asr, "ASRR_ZPmZ", 1>;
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defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr", "LSR_ZPZZ", int_aarch64_sve_lsr, "LSRR_ZPmZ", 1>;
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defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl", "LSL_ZPZZ", int_aarch64_sve_lsl, "LSLR_ZPmZ", 1>;
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defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr", "ASRR_ZPZZ", null_frag, "ASR_ZPmZ", 0>;
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defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr", "LSRR_ZPZZ", null_frag, "LSR_ZPmZ", 0>;
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defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr", "LSLR_ZPZZ", null_frag, "LSL_ZPmZ", 0>;
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defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr", int_aarch64_sve_asr_wide>;
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defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr", int_aarch64_sve_asr_wide>;
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defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr", int_aarch64_sve_lsr_wide>;
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defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr", int_aarch64_sve_lsr_wide>;
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@ -1777,10 +1782,10 @@ let Predicates = [HasSVE2] in {
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defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr", null_frag>;
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defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr", null_frag>;
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// SVE2 predicated shifts
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// SVE2 predicated shifts
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defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
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defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl", "SQSHL_ZPZI">;
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defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
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defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl", "UQSHL_ZPZI">;
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defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr", int_aarch64_sve_srshr>;
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defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr", "SRSHR_ZPZI", int_aarch64_sve_srshr>;
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defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr", int_aarch64_sve_urshr>;
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defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr", "URSHR_ZPZI", int_aarch64_sve_urshr>;
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defm SQSHLU_ZPmI : sve2_int_bin_pred_shift_imm_left< 0b1111, "sqshlu", int_aarch64_sve_sqshlu>;
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defm SQSHLU_ZPmI : sve2_int_bin_pred_shift_imm_left< 0b1111, "sqshlu", int_aarch64_sve_sqshlu>;
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// SVE2 integer add/subtract long
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// SVE2 integer add/subtract long
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@ -375,6 +375,12 @@ class SVE_3_Op_Pat_SelZero<ValueType vtd, SDPatternOperator op, ValueType vt1,
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ValueType vt2, ValueType vt3, Instruction inst>
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ValueType vt2, ValueType vt3, Instruction inst>
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: Pat<(vtd (vtd (op vt1:$Op1, (vselect vt1:$Op1, vt2:$Op2, (SVEDup0)), vt3:$Op3))),
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: Pat<(vtd (vtd (op vt1:$Op1, (vselect vt1:$Op1, vt2:$Op2, (SVEDup0)), vt3:$Op3))),
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(inst $Op1, $Op2, $Op3)>;
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(inst $Op1, $Op2, $Op3)>;
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class SVE_3_Op_Pat_Shift_Imm_SelZero<ValueType vtd, SDPatternOperator op,
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ValueType vt1, ValueType vt2,
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Operand vt3, Instruction inst>
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: Pat<(vtd (op vt1:$Op1, (vselect vt1:$Op1, vt2:$Op2, (SVEDup0)), (i32 (vt3:$Op3)))),
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(inst $Op1, $Op2, vt3:$Op3)>;
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}
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}
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//
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//
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@ -433,6 +439,13 @@ let hasNoSchedulingInfo = 1 in {
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Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
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Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
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let FalseLanes = flags;
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let FalseLanes = flags;
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}
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}
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class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
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FalseLanesEnum flags = FalseLanesNone>
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: SVEPseudo2Instr<name, 0>,
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Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
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let FalseLanes = flags;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -4692,19 +4705,23 @@ class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
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let Inst{4-0} = Zdn;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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let Constraints = "$Zdn = $_Zdn";
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let DestructiveInstType = DestructiveOther;
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let DestructiveInstType = DestructiveBinaryImm;
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let ElementSize = zprty.ElementSize;
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let ElementSize = zprty.ElementSize;
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}
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}
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multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> {
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multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm, string psName=""> {
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def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
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def _B : SVEPseudo2Instr<psName # _B, 1>,
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def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
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sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
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def _H : SVEPseudo2Instr<psName # _H, 1>,
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sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
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let Inst{8} = imm{3};
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let Inst{8} = imm{3};
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}
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}
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def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
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def _S : SVEPseudo2Instr<psName # _S, 1>,
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sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
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let Inst{9-8} = imm{4-3};
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let Inst{9-8} = imm{4-3};
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}
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}
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def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
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def _D : SVEPseudo2Instr<psName # _D, 1>,
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sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
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let Inst{22} = imm{5};
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let Inst{22} = imm{5};
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let Inst{9-8} = imm{4-3};
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let Inst{9-8} = imm{4-3};
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}
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}
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@ -4730,16 +4747,20 @@ multiclass sve2_int_bin_pred_shift_imm_left<bits<4> opc, string asm,
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def : SVE_3_Op_Imm_Pat<nxv2i64, op, nxv2i1, nxv2i64, i32, tvecshiftL64, !cast<Instruction>(NAME # _D)>;
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def : SVE_3_Op_Imm_Pat<nxv2i64, op, nxv2i1, nxv2i64, i32, tvecshiftL64, !cast<Instruction>(NAME # _D)>;
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}
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}
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multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm,
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multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm, string Ps,
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SDPatternOperator op = null_frag> {
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SDPatternOperator op = null_frag> {
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def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
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def _B : SVEPseudo2Instr<Ps # _B, 1>,
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def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
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sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
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def _H : SVEPseudo2Instr<Ps # _H, 1>,
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sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
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let Inst{8} = imm{3};
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let Inst{8} = imm{3};
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}
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}
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def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
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def _S : SVEPseudo2Instr<Ps # _S, 1>,
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sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
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let Inst{9-8} = imm{4-3};
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let Inst{9-8} = imm{4-3};
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}
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}
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def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
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def _D : SVEPseudo2Instr<Ps # _D, 1>,
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sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
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let Inst{22} = imm{5};
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let Inst{22} = imm{5};
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let Inst{9-8} = imm{4-3};
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let Inst{9-8} = imm{4-3};
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}
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}
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@ -4750,6 +4771,18 @@ multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm,
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def : SVE_3_Op_Imm_Pat<nxv2i64, op, nxv2i1, nxv2i64, i32, tvecshiftR64, !cast<Instruction>(NAME # _D)>;
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def : SVE_3_Op_Imm_Pat<nxv2i64, op, nxv2i1, nxv2i64, i32, tvecshiftR64, !cast<Instruction>(NAME # _D)>;
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}
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}
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multiclass sve_int_bin_pred_shift_0_right_zx<SDPatternOperator op = null_frag> {
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def _ZERO_B : PredTwoOpImmPseudo<NAME # _B, ZPR8, vecshiftR8, FalseLanesZero>;
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def _ZERO_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, vecshiftR16, FalseLanesZero>;
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def _ZERO_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, vecshiftR32, FalseLanesZero>;
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def _ZERO_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, vecshiftR64, FalseLanesZero>;
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def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv16i8, op, nxv16i1, nxv16i8, tvecshiftR8, !cast<Pseudo>(NAME # _ZERO_B)>;
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def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv8i16, op, nxv8i1, nxv8i16, tvecshiftR16, !cast<Pseudo>(NAME # _ZERO_H)>;
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def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv4i32, op, nxv4i1, nxv4i32, tvecshiftR32, !cast<Pseudo>(NAME # _ZERO_S)>;
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def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv2i64, op, nxv2i1, nxv2i64, tvecshiftR64, !cast<Pseudo>(NAME # _ZERO_D)>;
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}
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class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
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class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
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string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
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string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
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: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
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: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
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@ -4774,19 +4807,36 @@ class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
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let ElementSize = zprty.ElementSize;
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let ElementSize = zprty.ElementSize;
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}
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}
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multiclass sve_int_bin_pred_shift<bits<3> opc, string asm,
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multiclass sve_int_bin_pred_shift<bits<3> opc, string asm, string Ps,
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SDPatternOperator op> {
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SDPatternOperator op, string revname, bit isOrig> {
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def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>;
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let DestructiveInstType = DestructiveBinaryCommWithRev in {
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def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>;
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def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>,
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def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>;
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SVEPseudo2Instr<Ps # _B, 1>, SVEInstr2Rev<NAME # _B, revname # _B, isOrig>;
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def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>;
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def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>,
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SVEPseudo2Instr<Ps # _H, 1>, SVEInstr2Rev<NAME # _H, revname # _H, isOrig>;
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def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>,
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SVEPseudo2Instr<Ps # _S, 1>, SVEInstr2Rev<NAME # _S, revname # _S, isOrig>;
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def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>,
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SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isOrig>;
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}
|
||||||
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
|
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
|
||||||
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
|
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
|
||||||
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
|
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
|
||||||
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
|
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
multiclass sve_int_bin_pred_zx<SDPatternOperator op> {
|
||||||
|
def _ZERO_B : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesZero>;
|
||||||
|
def _ZERO_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>;
|
||||||
|
def _ZERO_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>;
|
||||||
|
def _ZERO_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesZero>;
|
||||||
|
|
||||||
|
def : SVE_3_Op_Pat_SelZero<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _ZERO_B)>;
|
||||||
|
def : SVE_3_Op_Pat_SelZero<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _ZERO_H)>;
|
||||||
|
def : SVE_3_Op_Pat_SelZero<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _ZERO_S)>;
|
||||||
|
def : SVE_3_Op_Pat_SelZero<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _ZERO_D)>;
|
||||||
|
}
|
||||||
|
|
||||||
multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm,
|
multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm,
|
||||||
SDPatternOperator op> {
|
SDPatternOperator op> {
|
||||||
def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>;
|
def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>;
|
||||||
|
340
test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll
Normal file
340
test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll
Normal file
@ -0,0 +1,340 @@
|
|||||||
|
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
|
||||||
|
|
||||||
|
;
|
||||||
|
; ASR
|
||||||
|
;
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||||
|
; CHECK-LABEL: asr_i8:
|
||||||
|
; CHECK: movprfx z0.b, p0/z, z0.b
|
||||||
|
; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
<vscale x 16 x i8> %b)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||||
|
; CHECK-LABEL: asr_i16:
|
||||||
|
; CHECK: movprfx z0.h, p0/z, z0.h
|
||||||
|
; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
<vscale x 8 x i16> %b)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||||
|
; CHECK-LABEL: asr_i32:
|
||||||
|
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||||
|
; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
<vscale x 4 x i32> %b)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: asr_i64:
|
||||||
|
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||||
|
; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
|
||||||
|
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg,
|
||||||
|
<vscale x 2 x i64> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 2 x i64> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @asr_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: asr_wide_i8:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: asr z0.b, p0/m, z0.b, z1.d
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.wide.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @asr_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: asr_wide_i16:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: asr z0.h, p0/m, z0.h, z1.d
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.wide.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @asr_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: asr_wide_i32:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: asr z0.s, p0/m, z0.s, z1.d
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.wide.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
;
|
||||||
|
; ASRD
|
||||||
|
;
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @asrd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||||
|
; CHECK-LABEL: asrd_i8:
|
||||||
|
; CHECK: movprfx z0.b, p0/z, z0.b
|
||||||
|
; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #1
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
i32 1)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @asrd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||||
|
; CHECK-LABEL: asrd_i16:
|
||||||
|
; CHECK: movprfx z0.h, p0/z, z0.h
|
||||||
|
; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #2
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
i32 2)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @asrd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||||
|
; CHECK-LABEL: asrd_i32:
|
||||||
|
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||||
|
; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #31
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
i32 31)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 2 x i64> @asrd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||||
|
; CHECK-LABEL: asrd_i64:
|
||||||
|
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||||
|
; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #64
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
|
||||||
|
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> %pg,
|
||||||
|
<vscale x 2 x i64> %a_z,
|
||||||
|
i32 64)
|
||||||
|
ret <vscale x 2 x i64> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
;
|
||||||
|
; LSL
|
||||||
|
;
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||||
|
; CHECK-LABEL: lsl_i8:
|
||||||
|
; CHECK: movprfx z0.b, p0/z, z0.b
|
||||||
|
; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
<vscale x 16 x i8> %b)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||||
|
; CHECK-LABEL: lsl_i16:
|
||||||
|
; CHECK: movprfx z0.h, p0/z, z0.h
|
||||||
|
; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
<vscale x 8 x i16> %b)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||||
|
; CHECK-LABEL: lsl_i32:
|
||||||
|
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||||
|
; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
<vscale x 4 x i32> %b)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsl_i64:
|
||||||
|
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||||
|
; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
|
||||||
|
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg,
|
||||||
|
<vscale x 2 x i64> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 2 x i64> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @lsl_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsl_wide_i8:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: lsl z0.b, p0/m, z0.b, z1.d
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.wide.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @lsl_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsl_wide_i16:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: lsl z0.h, p0/m, z0.h, z1.d
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.wide.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @lsl_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsl_wide_i32:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: lsl z0.s, p0/m, z0.s, z1.d
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.wide.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
;
|
||||||
|
; LSR
|
||||||
|
;
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||||
|
; CHECK-LABEL: lsr_i8:
|
||||||
|
; CHECK: movprfx z0.b, p0/z, z0.b
|
||||||
|
; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
<vscale x 16 x i8> %b)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||||
|
; CHECK-LABEL: lsr_i16:
|
||||||
|
; CHECK: movprfx z0.h, p0/z, z0.h
|
||||||
|
; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
<vscale x 8 x i16> %b)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||||
|
; CHECK-LABEL: lsr_i32:
|
||||||
|
; CHECK: movprfx z0.s, p0/z, z0.s
|
||||||
|
; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
<vscale x 4 x i32> %b)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsr_i64:
|
||||||
|
; CHECK: movprfx z0.d, p0/z, z0.d
|
||||||
|
; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
|
||||||
|
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg,
|
||||||
|
<vscale x 2 x i64> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 2 x i64> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 16 x i8> @lsr_wide_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsr_wide_i8:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: lsr z0.b, p0/m, z0.b, z1.d
|
||||||
|
%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
|
||||||
|
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.wide.nxv16i8(<vscale x 16 x i1> %pg,
|
||||||
|
<vscale x 16 x i8> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 16 x i8> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 8 x i16> @lsr_wide_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsr_wide_i16:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: lsr z0.h, p0/m, z0.h, z1.d
|
||||||
|
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
|
||||||
|
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.wide.nxv8i16(<vscale x 8 x i1> %pg,
|
||||||
|
<vscale x 8 x i16> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 8 x i16> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
define <vscale x 4 x i32> @lsr_wide_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
|
||||||
|
; CHECK-LABEL: lsr_wide_i32:
|
||||||
|
; CHECK-NOT: movprfx
|
||||||
|
; CHECK: lsr z0.s, p0/m, z0.s, z1.d
|
||||||
|
%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
|
||||||
|
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.wide.nxv4i32(<vscale x 4 x i1> %pg,
|
||||||
|
<vscale x 4 x i32> %a_z,
|
||||||
|
<vscale x 2 x i64> %b)
|
||||||
|
ret <vscale x 4 x i32> %out
|
||||||
|
}
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||||
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
|
||||||
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||||
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||||
|
declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||||
|
|
||||||
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
|
||||||
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
|
||||||
|
declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
|
Loading…
Reference in New Issue
Block a user