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[LoopVectorize] Precommit tests for D62510. NFC

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llvm-svn: 362060
This commit is contained in:
Craig Topper 2019-05-30 06:48:13 +00:00
parent d06b421172
commit b09f2479a1
2 changed files with 61 additions and 0 deletions
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26
test/Transforms/LoopVectorize/X86/fneg-cost.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -loop-vectorize -debug-only=loop-vectorize -S 2>&1 | FileCheck %s
; REQUIRES: asserts
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
; CHECK: Found an estimated cost of 2 for VF 1 For instruction: %neg = fneg float %{{.*}}
; CHECK: Found an estimated cost of 6 for VF 2 For instruction: %neg = fneg float %{{.*}}
; CHECK: Found an estimated cost of 14 for VF 4 For instruction: %neg = fneg float %{{.*}}
define void @fneg_cost(float* %a, i64 %n) {
entry:
br label %for.body
for.body: ; preds = %for.body.preheader, %for.body
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%arrayidx = getelementptr inbounds float, float* %a, i64 %indvars.iv
%0 = load float, float* %arrayidx, align 4
%neg = fneg float %0
store float %neg, float* %arrayidx, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp = icmp eq i64 %indvars.iv.next, %n
br i1 %cmp, label %for.end, label %for.body
for.end:
ret void
}

35
test/Transforms/LoopVectorize/fneg.ll Normal file
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; RUN: opt %s -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S | FileCheck %s
define void @foo(float* %a, i64 %n) {
; CHECK: vector.body:
; CHECK: [[WIDE_LOAD:%.*]] = load <4 x float>, <4 x float>* {{.*}}, align 4
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[WIDE_LOAD]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = fneg float [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[WIDE_LOAD]], i32 1
; CHECK-NEXT: [[TMP7:%.*]] = fneg float [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[WIDE_LOAD]], i32 2
; CHECK-NEXT: [[TMP9:%.*]] = fneg float [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[WIDE_LOAD]], i32 3
; CHECK-NEXT: [[TMP11:%.*]] = fneg float [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x float> undef, float [[TMP5]], i32 0
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x float> [[TMP12]], float [[TMP7]], i32 1
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[TMP9]], i32 2
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[TMP11]], i32 3
; CHECK: store <4 x float> [[TMP15]], <4 x float>* {{.*}}, align 4
;
entry:
br label %for.body
for.body:
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%arrayidx = getelementptr inbounds float, float* %a, i64 %indvars.iv
%0 = load float, float* %arrayidx, align 4
%sub = fneg float %0
store float %sub, float* %arrayidx, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp = icmp eq i64 %indvars.iv.next, %n
br i1 %cmp, label %for.exit, label %for.body
for.exit:
ret void
}