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[PowerPC] Support constrained fp operation for setcc

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The constrained fp operation fcmp was added by https://reviews.llvm.org/D69281.
This patch is trying to add the support for PowerPC backend.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D81727
This commit is contained in:
QingShan Zhang 2020-08-07 05:16:36 +00:00
parent f8c2a4c0d9
commit b0aa16911a
5 changed files with 2742 additions and 9 deletions
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8
include/llvm/Target/TargetSelectionDAG.td
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@ -553,6 +553,8 @@ def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP",
SDTIntToFPOp, [SDNPHasChain]>;
def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP",
SDTIntToFPOp, [SDNPHasChain]>;
def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>;
def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
def select : SDNode<"ISD::SELECT" , SDTSelect>;
@ -1420,6 +1422,12 @@ def any_sint_to_fp : PatFrags<(ops node:$src),
def any_uint_to_fp : PatFrags<(ops node:$src),
[(strict_uint_to_fp node:$src),
(uint_to_fp node:$src)]>;
def any_fsetcc : PatFrags<(ops node:$lhs, node:$rhs, node:$pred),
[(strict_fsetcc node:$lhs, node:$rhs, node:$pred),
(setcc node:$lhs, node:$rhs, node:$pred)]>;
def any_fsetccs : PatFrags<(ops node:$lhs, node:$rhs, node:$pred),
[(strict_fsetccs node:$lhs, node:$rhs, node:$pred),
(setcc node:$lhs, node:$rhs, node:$pred)]>;
multiclass binary_atomic_op_ord<SDNode atomic_op> {
def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),

2
lib/Target/PowerPC/P9InstrResources.td
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@ -94,7 +94,7 @@ def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_3SLOTS_1C],
(instregex "CMPRB(8)?$"),
(instregex "TD(I)?$"),
(instregex "TW(I)?$"),
(instregex "FCMPU(S|D)$"),
(instregex "FCMP(O|U)(S|D)$"),
(instregex "XSTSTDC(S|D)P$"),
FTDIV,
FTSQRT,

10
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -419,6 +419,16 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
if (!Subtarget.useCRBits())
setOperationAction(ISD::SETCC, MVT::i32, Custom);
if (Subtarget.hasFPU()) {
setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
}
// PowerPC does not have BRCOND which requires SetCC
if (!Subtarget.useCRBits())
setOperationAction(ISD::BRCOND, MVT::Other, Expand);

32
lib/Target/PowerPC/PPCInstrInfo.td
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@ -2570,14 +2570,17 @@ let isCompare = 1, hasSideEffects = 0 in {
}
}
let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations.
//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
// "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
let isCompare = 1, hasSideEffects = 0 in {
def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
"fcmpo $crD, $fA, $fB", IIC_FPCompare>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
"fcmpu $crD, $fA, $fB", IIC_FPCompare>;
def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
"fcmpo $crD, $fA, $fB", IIC_FPCompare>;
}
}
def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
@ -3934,14 +3937,27 @@ multiclass FSetCCPat<SDNode SetCC, ValueType Ty, PatLeaf FCmp> {
}
let Predicates = [HasFPU] in {
// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set.
// SETCC for f32.
defm : FSetCCPat<setcc, f32, FCMPUS>;
defm : FSetCCPat<any_fsetcc, f32, FCMPUS>;
// SETCC for f64.
defm : FSetCCPat<setcc, f64, FCMPUD>;
defm : FSetCCPat<any_fsetcc, f64, FCMPUD>;
// SETCC for f128.
defm : FSetCCPat<setcc, f128, XSCMPUQP>;
defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>;
// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and,
// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN,
// then VXVC is set.
// SETCCS for f32.
defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>;
// SETCCS for f64.
defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>;
// SETCCS for f128.
defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>;
}
// This must be in this file because it relies on patterns defined in this file

2699
test/CodeGen/PowerPC/fp-strict-fcmp.ll Normal file
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