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[PowerPC] Semachecking for XL compat builtin icbt

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This patch is in a series of patches to provide builtins for compatibility with the XL compiler.
This patch adds semachecking for an already implemented builtin, `__icbt`. `__icbt` is only
valid for Power8 and up.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D105834
This commit is contained in:
Quinn Pham 2021-07-20 09:42:14 -05:00 committed by Kamau Bridgeman
parent 95c86f6829
commit b0ba22b69f
3 changed files with 0 additions and 17 deletions
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1
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -1534,7 +1534,6 @@ let TargetPrefix = "ppc" in {
[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
def int_ppc_dcbz : GCCBuiltin<"__builtin_ppc_dcbz">,
Intrinsic<[], [llvm_ptr_ty], []>;
// FIXME: __icbt is only valid for pwr8 and up.
def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
Intrinsic<[], [llvm_ptr_ty], []>;

15
test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
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@ -60,18 +60,3 @@ entry:
ret void
}
declare void @llvm.ppc.iospace.sync()
; FIXME: __icbt is only valid for pwr8 and up.
define dso_local void @test_builtin_ppc_icbt() {
; CHECK-LABEL: test_builtin_ppc_icbt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 3, -8(1)
; CHECK-NEXT: icbt 0, 0, 3
; CHECK-NEXT: blr
entry:
%a = alloca i8*, align 8
%0 = load i8*, i8** %a, align 8
call void @llvm.ppc.icbt(i8* %0)
ret void
}
declare void @llvm.ppc.icbt(i8*)

1
test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
View File

@ -94,7 +94,6 @@ entry:
}
declare void @llvm.ppc.iospace.sync()
; FIXME: __icbt is only valid for pwr8 and up.
define dso_local void @test_builtin_ppc_icbt() {
; CHECK-LABEL: test_builtin_ppc_icbt:
; CHECK: # %bb.0: # %entry