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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing.
Summary: Don't peel of the offset if the resulting base could possibly be negative in Indirect addressing. This is because the M0 field is of unsigned. This patch achieves the similar goal as https://reviews.llvm.org/D55241, but keeps the optimization if the base is known unsigned. Reviewers: arsemn Differential Revision: https://reviews.llvm.org/D55568 llvm-svn: 349951
This commit is contained in:
Changpeng Fang
parent
bf3176552a
commit
b0f778424c
@ -1454,9 +1454,13 @@ bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
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ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
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// (add n0, c0)
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Base = N0;
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Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
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return true;
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// Don't peel off the offset (c0) if doing so could possibly lead
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// the base (n0) to be negative.
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if (C1->getSExtValue() <= 0 || CurDAG->SignBitIsZero(N0)) {
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Base = N0;
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Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
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return true;
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}
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}
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if (isa<ConstantSDNode>(Index))
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@ -14,8 +14,9 @@
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; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
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; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
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; GCN-DAG: v_add_u32_e32 [[IDX1:v[0-9]+]], 1, [[IDX0]]
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; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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@ -36,8 +37,8 @@
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; GCN: s_mov_b64 [[MASK]], exec
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; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX1]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX1]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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@ -17,8 +17,9 @@
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; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
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; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
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; GCN-DAG: v_add_{{i32|u32}}_e32 [[IDX1:v[0-9]+]], vcc, 1, [[IDX0]]
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; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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@ -39,8 +40,8 @@
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; GCN: s_mov_b64 [[MASK]], exec
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; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX1]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX1]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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@ -7,11 +7,12 @@
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; indexing of vectors.
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; GCN-LABEL: {{^}}extract_w_offset:
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; GCN-DAG: s_load_dword [[IN:s[0-9]+]]
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; GCN-DAG: s_load_dword [[IN0:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
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; GCN-DAG: v_mov_b32_e32 [[BASEREG:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 1.0
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
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; GCN-DAG: v_mov_b32_e32 [[BASEREG:v[0-9]+]], 1.0
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; GCN-DAG: s_add_i32 [[IN:s[0-9]+]], [[IN0]], 1
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; MOVREL-DAG: s_mov_b32 m0, [[IN]]
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; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, [[BASEREG]]
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@ -29,16 +30,17 @@ entry:
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; XXX: Could do v_or_b32 directly
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; GCN-LABEL: {{^}}extract_w_offset_salu_use_vector:
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; GCN-DAG: s_or_b32
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; GCN-DAG: s_or_b32
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; GCN-DAG: s_or_b32
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; GCN-DAG: s_or_b32
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; MOVREL: s_mov_b32 m0
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; GCN-DAG: s_or_b32
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; GCN-DAG: s_or_b32
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; GCN-DAG: s_or_b32
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; GCN-DAG: s_or_b32
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; MOVREL: v_movrels_b32_e32
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; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, src0{{$}}
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@ -176,7 +178,8 @@ entry:
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}
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; GCN-LABEL: {{^}}insert_w_offset:
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; GCN-DAG: s_load_dword [[IN:s[0-9]+]]
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; GCN-DAG: s_load_dword [[IN0:s[0-9]+]]
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; MOVREL-DAG: s_add_i32 [[IN:s[0-9]+]], [[IN0]], 1
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; MOVREL-DAG: s_mov_b32 m0, [[IN]]
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; GCN-DAG: v_mov_b32_e32 v[[ELT0:[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 v[[ELT1:[0-9]+]], 2.0
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@ -185,7 +188,7 @@ entry:
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; GCN-DAG: v_mov_b32_e32 v[[ELT15:[0-9]+]], 0x41800000
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; GCN-DAG: v_mov_b32_e32 v[[INS:[0-9]+]], 0x41880000
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; MOVREL: v_movreld_b32_e32 v[[ELT1]], v[[INS]]
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; MOVREL: v_movreld_b32_e32 v[[ELT0]], v[[INS]]
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; MOVREL: buffer_store_dwordx4 v{{\[}}[[ELT0]]:[[ELT3]]{{\]}}
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define amdgpu_kernel void @insert_w_offset(<16 x float> addrspace(1)* %out, i32 %in) {
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entry:
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@ -195,6 +198,51 @@ entry:
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ret void
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}
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; GCN-LABEL: {{^}}insert_unsigned_base_plus_offset:
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; GCN-DAG: s_load_dword [[IN:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 2.0
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; GCN-DAG: s_and_b32 [[BASE:s[0-9]+]], [[IN]], 0xffff
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; MOVREL: s_mov_b32 m0, [[BASE]]
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; MOVREL: v_movreld_b32_e32 [[ELT1]], v{{[0-9]+}}
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; IDXMODE: s_set_gpr_idx_on [[BASE]], dst
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; IDXMODE-NEXT: v_mov_b32_e32 [[ELT1]], v{{[0-9]+}}
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; IDXMODE-NEXT: s_set_gpr_idx_off
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define amdgpu_kernel void @insert_unsigned_base_plus_offset(<16 x float> addrspace(1)* %out, i16 %in) {
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entry:
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%base = zext i16 %in to i32
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%add = add i32 %base, 1
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%ins = insertelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, float 17.0, i32 %add
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store <16 x float> %ins, <16 x float> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}insert_signed_base_plus_offset:
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; GCN-DAG: s_load_dword [[IN:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 2.0
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; GCN-DAG: s_sext_i32_i16 [[BASE:s[0-9]+]], [[IN]]
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; GCN-DAG: s_add_i32 [[BASE_PLUS_OFFSET:s[0-9]+]], [[BASE]], 1
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; MOVREL: s_mov_b32 m0, [[BASE_PLUS_OFFSET]]
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; MOVREL: v_movreld_b32_e32 [[ELT0]], v{{[0-9]+}}
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; IDXMODE: s_set_gpr_idx_on [[BASE_PLUS_OFFSET]], dst
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; IDXMODE-NEXT: v_mov_b32_e32 [[ELT0]], v{{[0-9]+}}
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; IDXMODE-NEXT: s_set_gpr_idx_off
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define amdgpu_kernel void @insert_signed_base_plus_offset(<16 x float> addrspace(1)* %out, i16 %in) {
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entry:
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%base = sext i16 %in to i32
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%add = add i32 %base, 1
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%ins = insertelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, float 17.0, i32 %add
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store <16 x float> %ins, <16 x float> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}insert_wo_offset:
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; GCN: s_load_dword [[IN:s[0-9]+]]
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@ -354,8 +402,12 @@ entry:
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; GCN: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec
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; GCN: s_waitcnt vmcnt(0)
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; PREGFX9: v_add_{{i32|u32}}_e32 [[IDX1:v[0-9]+]], vcc, 1, [[IDX0]]
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; GFX9: v_add_{{i32|u32}}_e32 [[IDX1:v[0-9]+]], 1, [[IDX0]]
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; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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@ -373,20 +425,20 @@ entry:
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; FIXME: Redundant copy
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; GCN: s_mov_b64 exec, [[MASK]]
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; GCN: v_mov_b32_e32 [[VEC_ELT1_2:v[0-9]+]], [[S_ELT1]]
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; GCN: v_mov_b32_e32 [[VEC_ELT0_2:v[0-9]+]], [[S_ELT0]]
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; GCN: s_mov_b64 [[MASK2:s\[[0-9]+:[0-9]+\]]], exec
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; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX1]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX1]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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; MOVREL-NEXT: v_movrels_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT1_2]]
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; MOVREL-NEXT: v_movrels_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT0_2]]
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; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0
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; IDXMODE-NEXT: v_mov_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT1_2]]
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; IDXMODE-NEXT: v_mov_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT0_2]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN-NEXT: s_xor_b64 exec, exec, vcc
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@ -492,13 +544,15 @@ bb:
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; offset puts outside of superegister bounaries, so clamp to 1st element.
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; GCN-LABEL: {{^}}extract_largest_inbounds_offset:
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; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]{{\].* offset:48}}
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; GCN-DAG: s_load_dword [[IDX:s[0-9]+]]
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; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]
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; GCN-DAG: s_load_dword [[IDX0:s[0-9]+]]
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; GCN-DAG: s_add_i32 [[IDX:s[0-9]+]], [[IDX0]], 15
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; MOVREL: s_mov_b32 m0, [[IDX]]
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; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[HI_ELT]]
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; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
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; IDXMODE: s_set_gpr_idx_on [[IDX]], src0
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; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[HI_ELT]]
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; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN: buffer_store_dword [[EXTRACT]]
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@ -514,10 +568,11 @@ entry:
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; GCN-LABEL: {{^}}extract_out_of_bounds_offset:
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; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]{{\]}}
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; GCN-DAG: s_load_dword [[IDX:s[0-9]+]]
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; MOVREL: s_add_i32 m0, [[IDX]], 16
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; GCN: s_add_i32 [[ADD_IDX:s[0-9]+]], [[IDX]], 16
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; MOVREL: s_mov_b32 m0, [[ADD_IDX]]
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; MOVREL: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
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; IDXMODE: s_add_i32 [[ADD_IDX:s[0-9]+]], [[IDX]], 16
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; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], src0
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; IDXMODE: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]]
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; IDXMODE: s_set_gpr_idx_off
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@ -532,18 +587,15 @@ entry:
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ret void
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}
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; Test that the or is folded into the base address register instead of
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; added to m0
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; GCN-LABEL: {{^}}extractelement_v16i32_or_index:
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; GCN: s_load_dword [[IDX_IN:s[0-9]+]]
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; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]]
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; GCN-NOT: [[IDX_SHL]]
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; GCN: s_or_b32 [[IDX_FIN:s[0-9]+]], [[IDX_SHL]], 1
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; MOVREL: s_mov_b32 m0, [[IDX_SHL]]
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; MOVREL: s_mov_b32 m0, [[IDX_FIN]]
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; MOVREL: v_movrels_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; IDXMODE: s_set_gpr_idx_on [[IDX_SHL]], src0
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; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], src0
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; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; IDXMODE: s_set_gpr_idx_off
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define amdgpu_kernel void @extractelement_v16i32_or_index(i32 addrspace(1)* %out, <16 x i32> addrspace(1)* %in, i32 %idx.in) {
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@ -559,12 +611,12 @@ entry:
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; GCN-LABEL: {{^}}insertelement_v16f32_or_index:
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; GCN: s_load_dword [[IDX_IN:s[0-9]+]]
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; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]]
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; GCN-NOT: [[IDX_SHL]]
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; GCN: s_or_b32 [[IDX_FIN:s[0-9]+]], [[IDX_SHL]], 1
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; MOVREL: s_mov_b32 m0, [[IDX_SHL]]
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; MOVREL: s_mov_b32 m0, [[IDX_FIN]]
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; MOVREL: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; IDXMODE: s_set_gpr_idx_on [[IDX_SHL]], dst
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; IDXMODE: s_set_gpr_idx_on [[IDX_FIN]], dst
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; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; IDXMODE: s_set_gpr_idx_off
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define amdgpu_kernel void @insertelement_v16f32_or_index(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %idx.in) nounwind {
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