RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00
Code Issues Projects Releases Wiki Activity

[TableGen] Correct the shift to the proper bit width.

Browse Source 
- Replace the previous 32-bit shift with 64-bit one matching `OpInit`.

llvm-svn: 368513
This commit is contained in:
Michael Liao 2019-08-10 16:15:06 +00:00
parent 691f754300
commit b0f9c14a99
2 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
test/TableGen/FixedLenDecoderEmitter/InitValue.td
View File

@ -28,8 +28,19 @@ def bar : Instruction {
let Inst{15-8} = factor{7-0};
}
def bax : Instruction {
let InOperandList = (ins i32imm:$factor);
field bits<16> Inst;
field bits<16> SoftFail = 0;
bits<33> factor;
let factor{32} = 1; // non-zero initial value
let Inst{15-8} = factor{32-25};
}
}
// CHECK: tmp = fieldFromInstruction(insn, 9, 7) << 1;
// CHECK: tmp = 0x1;
// CHECK: tmp |= fieldFromInstruction(insn, 9, 7) << 1;
// CHECK: tmp = 0x100000000;
// CHECK: tmp |= fieldFromInstruction(insn, 8, 7) << 25;

2
utils/TableGen/FixedLenDecoderEmitter.cpp
View File

@ -2038,7 +2038,7 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
for (unsigned I = 0; I < OpBits->getNumBits(); ++I)
if (const BitInit *OpBit = dyn_cast<BitInit>(OpBits->getBit(I)))
if (OpBit->getValue())
OpInfo.InitValue |= 1 << I;
OpInfo.InitValue |= 1ULL << I;
unsigned Base = ~0U;
unsigned Width = 0;