mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
[MIPS GlobalISel] Select float and double phi
Select float and double phi for MIPS32. Differential Revision: https://reviews.llvm.org/D64420 llvm-svn: 365627
This commit is contained in:
Petar Avramovic
parent
a669e1e1ef
commit
b0ff3da4d4
@ -41,6 +41,9 @@ private:
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bool materialize32BitImm(Register DestReg, APInt Imm,
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MachineIRBuilder &B) const;
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bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
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const TargetRegisterClass *
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getRegClassForTypeOnBank(unsigned OpSize, const RegisterBank &RB,
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const RegisterBankInfo &RBI) const;
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const MipsTargetMachine &TM;
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const MipsSubtarget &STI;
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@ -104,6 +107,22 @@ bool MipsInstructionSelector::selectCopy(MachineInstr &I,
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return true;
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}
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const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank(
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unsigned OpSize, const RegisterBank &RB,
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const RegisterBankInfo &RBI) const {
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if (RB.getID() == Mips::GPRBRegBankID)
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return &Mips::GPR32RegClass;
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if (RB.getID() == Mips::FPRBRegBankID)
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return OpSize == 32
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? &Mips::FGR32RegClass
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: STI.hasMips32r6() || STI.isFP64bit() ? &Mips::FGR64RegClass
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: &Mips::AFGR64RegClass;
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llvm_unreachable("getRegClassForTypeOnBank can't find register class.");
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return nullptr;
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}
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bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
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MachineIRBuilder &B) const {
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assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
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@ -262,13 +281,15 @@ bool MipsInstructionSelector::select(MachineInstr &I,
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}
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case G_PHI: {
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const Register DestReg = I.getOperand(0).getReg();
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const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
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const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
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if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
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return false;
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const TargetRegisterClass *DefRC = nullptr;
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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DefRC = TRI.getRegClass(DestReg);
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else
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DefRC = getRegClassForTypeOnBank(OpSize,
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*RBI.getRegBank(DestReg, MRI, TRI), RBI);
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const TargetRegisterClass *DefRC = &Mips::GPR32RegClass;
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I.setDesc(TII.get(TargetOpcode::PHI));
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return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
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}
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@ -1,8 +1,9 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
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--- |
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define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
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define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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@ -17,34 +18,99 @@
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ret i32 %cond
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}
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define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
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ret i64 %cond
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}
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define float @phi_float(i1 %cnd, float %a, float %b) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
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ret float %cond
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}
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define double @phi_double(double %a, double %b, i1 %cnd) {
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entry:
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br i1 %cnd, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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br label %cond.end
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cond.false: ; preds = %entry
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
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ret double %cond
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}
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...
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---
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name: test_i32
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name: phi_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: test_i32
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; MIPS32: bb.0.entry:
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; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32: J %bb.2, implicit-def $at
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; MIPS32: bb.1.cond.true:
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; MIPS32: successors: %bb.3(0x80000000)
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; MIPS32: J %bb.3, implicit-def $at
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; MIPS32: bb.2.cond.false:
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; MIPS32: successors: %bb.3(0x80000000)
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; MIPS32: bb.3.cond.end:
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; MIPS32: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32: $v0 = COPY [[PHI]]
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; MIPS32: RetRA implicit $v0
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; MIPS32FP32-LABEL: name: phi_i32
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $a0, $a1, $a2
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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; MIPS32FP32: bb.2.cond.false:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: bb.3.cond.end:
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; MIPS32FP32: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32FP32: $v0 = COPY [[PHI]]
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; MIPS32FP32: RetRA implicit $v0
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; MIPS32FP64-LABEL: name: phi_i32
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; MIPS32FP64: bb.0.entry:
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; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $a0, $a1, $a2
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32FP64: J %bb.2, implicit-def $at
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; MIPS32FP64: bb.1.cond.true:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: J %bb.3, implicit-def $at
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; MIPS32FP64: bb.2.cond.false:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: bb.3.cond.end:
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; MIPS32FP64: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
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; MIPS32FP64: $v0 = COPY [[PHI]]
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; MIPS32FP64: RetRA implicit $v0
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bb.1.entry:
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liveins: $a0, $a1, $a2
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@ -68,3 +134,239 @@ body: |
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RetRA implicit $v0
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...
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---
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name: phi_i64
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true }
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- { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
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body: |
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; MIPS32FP32-LABEL: name: phi_i64
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $a0, $a2, $a3
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
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; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
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; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
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; MIPS32FP32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
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; MIPS32FP32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
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; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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; MIPS32FP32: bb.2.cond.false:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: bb.3.cond.end:
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; MIPS32FP32: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
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; MIPS32FP32: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
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; MIPS32FP32: $v0 = COPY [[PHI]]
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; MIPS32FP32: $v1 = COPY [[PHI1]]
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; MIPS32FP32: RetRA implicit $v0, implicit $v1
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; MIPS32FP64-LABEL: name: phi_i64
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; MIPS32FP64: bb.0.entry:
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; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $a0, $a2, $a3
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
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; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
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; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
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; MIPS32FP64: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
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; MIPS32FP64: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
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; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32FP64: J %bb.2, implicit-def $at
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; MIPS32FP64: bb.1.cond.true:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: J %bb.3, implicit-def $at
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; MIPS32FP64: bb.2.cond.false:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: bb.3.cond.end:
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; MIPS32FP64: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
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; MIPS32FP64: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
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; MIPS32FP64: $v0 = COPY [[PHI]]
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; MIPS32FP64: $v1 = COPY [[PHI1]]
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; MIPS32FP64: RetRA implicit $v0, implicit $v1
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bb.1.entry:
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liveins: $a0, $a2, $a3
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%3:gprb(s32) = COPY $a0
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%4:gprb(s32) = COPY $a2
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%5:gprb(s32) = COPY $a3
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%8:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
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%6:gprb(s32) = G_LOAD %8(p0) :: (load 4 from %fixed-stack.1, align 8)
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%9:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
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%7:gprb(s32) = G_LOAD %9(p0) :: (load 4 from %fixed-stack.0)
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%14:gprb(s32) = G_CONSTANT i32 1
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%15:gprb(s32) = COPY %3(s32)
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%13:gprb(s32) = G_AND %15, %14
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G_BRCOND %13(s32), %bb.2
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G_BR %bb.3
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bb.2.cond.true:
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G_BR %bb.4
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bb.3.cond.false:
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bb.4.cond.end:
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%20:gprb(s32) = G_PHI %4(s32), %bb.2, %6(s32), %bb.3
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%21:gprb(s32) = G_PHI %5(s32), %bb.2, %7(s32), %bb.3
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$v0 = COPY %20(s32)
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$v1 = COPY %21(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: phi_float
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; MIPS32FP32-LABEL: name: phi_float
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; MIPS32FP32: bb.0.entry:
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; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP32: liveins: $a0, $a1, $a2
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
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; MIPS32FP32: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
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; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32FP32: J %bb.2, implicit-def $at
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; MIPS32FP32: bb.1.cond.true:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: J %bb.3, implicit-def $at
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; MIPS32FP32: bb.2.cond.false:
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; MIPS32FP32: successors: %bb.3(0x80000000)
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; MIPS32FP32: bb.3.cond.end:
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; MIPS32FP32: [[PHI:%[0-9]+]]:fgr32 = PHI [[MTC1_]], %bb.1, [[MTC1_1]], %bb.2
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; MIPS32FP32: $f0 = COPY [[PHI]]
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; MIPS32FP32: RetRA implicit $f0
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; MIPS32FP64-LABEL: name: phi_float
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; MIPS32FP64: bb.0.entry:
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; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32FP64: liveins: $a0, $a1, $a2
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
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; MIPS32FP64: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
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; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
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; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32FP64: J %bb.2, implicit-def $at
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; MIPS32FP64: bb.1.cond.true:
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; MIPS32FP64: successors: %bb.3(0x80000000)
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; MIPS32FP64: J %bb.3, implicit-def $at
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; MIPS32FP64: bb.2.cond.false:
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; MIPS32FP64: successors: %bb.3(0x80000000)
|
||||
; MIPS32FP64: bb.3.cond.end:
|
||||
; MIPS32FP64: [[PHI:%[0-9]+]]:fgr32 = PHI [[MTC1_]], %bb.1, [[MTC1_1]], %bb.2
|
||||
; MIPS32FP64: $f0 = COPY [[PHI]]
|
||||
; MIPS32FP64: RetRA implicit $f0
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2
|
||||
|
||||
%3:gprb(s32) = COPY $a0
|
||||
%1:fgr32(s32) = MTC1 $a1
|
||||
%2:fgr32(s32) = MTC1 $a2
|
||||
%6:gprb(s32) = G_CONSTANT i32 1
|
||||
%7:gprb(s32) = COPY %3(s32)
|
||||
%5:gprb(s32) = G_AND %7, %6
|
||||
G_BRCOND %5(s32), %bb.2
|
||||
G_BR %bb.3
|
||||
|
||||
bb.2.cond.true:
|
||||
G_BR %bb.4
|
||||
|
||||
bb.3.cond.false:
|
||||
|
||||
bb.4.cond.end:
|
||||
%4:fprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
|
||||
$f0 = COPY %4(s32)
|
||||
RetRA implicit $f0
|
||||
|
||||
...
|
||||
---
|
||||
name: phi_double
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
fixedStack:
|
||||
- { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
|
||||
body: |
|
||||
; MIPS32FP32-LABEL: name: phi_double
|
||||
; MIPS32FP32: bb.0.entry:
|
||||
; MIPS32FP32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; MIPS32FP32: liveins: $d6, $d7
|
||||
; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
|
||||
; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
|
||||
; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
|
||||
; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
|
||||
; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
|
||||
; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
|
||||
; MIPS32FP32: BNE [[AND]], $zero, %bb.1, implicit-def $at
|
||||
; MIPS32FP32: J %bb.2, implicit-def $at
|
||||
; MIPS32FP32: bb.1.cond.true:
|
||||
; MIPS32FP32: successors: %bb.3(0x80000000)
|
||||
; MIPS32FP32: J %bb.3, implicit-def $at
|
||||
; MIPS32FP32: bb.2.cond.false:
|
||||
; MIPS32FP32: successors: %bb.3(0x80000000)
|
||||
; MIPS32FP32: bb.3.cond.end:
|
||||
; MIPS32FP32: [[PHI:%[0-9]+]]:afgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
|
||||
; MIPS32FP32: $d0 = COPY [[PHI]]
|
||||
; MIPS32FP32: RetRA implicit $d0
|
||||
; MIPS32FP64-LABEL: name: phi_double
|
||||
; MIPS32FP64: bb.0.entry:
|
||||
; MIPS32FP64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; MIPS32FP64: liveins: $d6, $d7
|
||||
; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
|
||||
; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
|
||||
; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
|
||||
; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
|
||||
; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
|
||||
; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
|
||||
; MIPS32FP64: BNE [[AND]], $zero, %bb.1, implicit-def $at
|
||||
; MIPS32FP64: J %bb.2, implicit-def $at
|
||||
; MIPS32FP64: bb.1.cond.true:
|
||||
; MIPS32FP64: successors: %bb.3(0x80000000)
|
||||
; MIPS32FP64: J %bb.3, implicit-def $at
|
||||
; MIPS32FP64: bb.2.cond.false:
|
||||
; MIPS32FP64: successors: %bb.3(0x80000000)
|
||||
; MIPS32FP64: bb.3.cond.end:
|
||||
; MIPS32FP64: [[PHI:%[0-9]+]]:fgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
|
||||
; MIPS32FP64: $d0 = COPY [[PHI]]
|
||||
; MIPS32FP64: RetRA implicit $d0
|
||||
bb.1.entry:
|
||||
liveins: $d6, $d7
|
||||
|
||||
%0:fprb(s64) = COPY $d6
|
||||
%1:fprb(s64) = COPY $d7
|
||||
%4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
%3:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
|
||||
%7:gprb(s32) = G_CONSTANT i32 1
|
||||
%8:gprb(s32) = COPY %3(s32)
|
||||
%6:gprb(s32) = G_AND %8, %7
|
||||
G_BRCOND %6(s32), %bb.2
|
||||
G_BR %bb.3
|
||||
|
||||
bb.2.cond.true:
|
||||
G_BR %bb.4
|
||||
|
||||
bb.3.cond.false:
|
||||
|
||||
bb.4.cond.end:
|
||||
%5:fprb(s64) = G_PHI %0(s64), %bb.2, %1(s64), %bb.3
|
||||
$d0 = COPY %5(s64)
|
||||
RetRA implicit $d0
|
||||
|
||||
...
|
||||
|
||||
@ -221,3 +221,89 @@ cond.end:
|
||||
%cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
|
||||
ret i64 %cond
|
||||
}
|
||||
|
||||
define float @phi_float(i1 %cnd, float %a, float %b) {
|
||||
; MIPS32-LABEL: phi_float:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -16
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 16
|
||||
; MIPS32-NEXT: mtc1 $5, $f0
|
||||
; MIPS32-NEXT: mtc1 $6, $f1
|
||||
; MIPS32-NEXT: ori $1, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $4, $1
|
||||
; MIPS32-NEXT: swc1 $f0, 12($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: swc1 $f1, 8($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: bnez $1, $BB5_2
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: # %bb.1: # %entry
|
||||
; MIPS32-NEXT: j $BB5_3
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: $BB5_2: # %cond.true
|
||||
; MIPS32-NEXT: lwc1 $f0, 12($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: swc1 $f0, 4($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: j $BB5_4
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: $BB5_3: # %cond.false
|
||||
; MIPS32-NEXT: lwc1 $f0, 8($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: swc1 $f0, 4($sp) # 4-byte Folded Spill
|
||||
; MIPS32-NEXT: $BB5_4: # %cond.end
|
||||
; MIPS32-NEXT: lwc1 $f0, 4($sp) # 4-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
br i1 %cnd, label %cond.true, label %cond.false
|
||||
|
||||
cond.true:
|
||||
br label %cond.end
|
||||
|
||||
cond.false:
|
||||
br label %cond.end
|
||||
|
||||
cond.end:
|
||||
%cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
|
||||
ret float %cond
|
||||
}
|
||||
|
||||
define double @phi_double(double %a, double %b, i1 %cnd) {
|
||||
; MIPS32-LABEL: phi_double:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addiu $sp, $sp, -24
|
||||
; MIPS32-NEXT: .cfi_def_cfa_offset 24
|
||||
; MIPS32-NEXT: addiu $1, $sp, 40
|
||||
; MIPS32-NEXT: lw $1, 0($1)
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: sdc1 $f12, 16($sp) # 8-byte Folded Spill
|
||||
; MIPS32-NEXT: sdc1 $f14, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS32-NEXT: bnez $1, $BB6_2
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: # %bb.1: # %entry
|
||||
; MIPS32-NEXT: j $BB6_3
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: $BB6_2: # %cond.true
|
||||
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
|
||||
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
|
||||
; MIPS32-NEXT: j $BB6_4
|
||||
; MIPS32-NEXT: nop
|
||||
; MIPS32-NEXT: $BB6_3: # %cond.false
|
||||
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
|
||||
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
|
||||
; MIPS32-NEXT: $BB6_4: # %cond.end
|
||||
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
|
||||
; MIPS32-NEXT: addiu $sp, $sp, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
br i1 %cnd, label %cond.true, label %cond.false
|
||||
|
||||
cond.true:
|
||||
br label %cond.end
|
||||
|
||||
cond.false:
|
||||
br label %cond.end
|
||||
|
||||
cond.end:
|
||||
%cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
|
||||
ret double %cond
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user