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[mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions

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Differential Revision: http://reviews.llvm.org/D9189

llvm-svn: 247780
This commit is contained in:
Zoran Jovanovic 2015-09-16 09:14:35 +00:00
parent 67609bcb7c
commit b115382747
13 changed files with 141 additions and 4 deletions
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5
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -947,6 +947,10 @@ public:
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
&& getMemBase()->isGPRAsmReg();
}
template <unsigned Bits> bool isMemWithSimmOffsetGPR() const {
return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff()) &&
getMemBase()->isGPRAsmReg();
}
bool isMemWithGRPMM16Base() const {
return isMem() && getMemBase()->isMM16AsmReg();
}
@ -1758,6 +1762,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if (Imm < 0 || Imm > 60 || (Imm % 4 != 0))
return Error(IDLoc, "immediate operand value out of range");
break;
case Mips::PREFX_MM:
case Mips::CACHE:
case Mips::PREF:
Opnd = Inst.getOperand(2);

31
lib/Target/Mips/MicroMipsInstrFormats.td
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@ -389,6 +389,22 @@ class LW_FM_MM<bits<6> op> : MMArch {
let Inst{15-0} = addr{15-0};
}
class POOL32C_LHUE_FM_MM<bits<6> op, bits<4> fmt, bits<3> funct> : MMArch {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
bits<9> offset = addr{8-0};
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rt;
let Inst{20-16} = base;
let Inst{15-12} = fmt;
let Inst{11-9} = funct;
let Inst{8-0} = offset;
}
class LWL_FM_MM<bits<4> funct> {
bits<5> rt;
bits<21> addr;
@ -938,6 +954,21 @@ class CACHE_PREFE_FM_MM<bits<6> op, bits<3> funct> : MMArch {
let Inst{8-0} = offset;
}
class POOL32F_PREFX_FM_MM<bits<6> op, bits<9> funct> : MMArch {
bits<5> index;
bits<5> base;
bits<5> hint;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = index;
let Inst{20-16} = base;
let Inst{15-11} = hint;
let Inst{10-9} = 0x0;
let Inst{8-0} = funct;
}
class BARRIER_FM_MM<bits<5> op> : MMArch {
bits<32> Inst;

18
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -484,6 +484,10 @@ class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
!strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
class PrefetchIndexed<string opstr> :
InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
!strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
class AddImmUPC<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
!strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
@ -713,6 +717,18 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
}
let DecoderMethod = "DecodeMemMMImm9" in {
def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
}
def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
@ -890,6 +906,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
}
let Predicates = [InMicroMips] in {

23
lib/Target/Mips/MipsInstrInfo.td
View File

@ -466,6 +466,14 @@ def MipsMemSimm9AsmOperand : AsmOperandClass {
let PredicateMethod = "isMemWithSimmOffset<9>";
}
def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm9GPR";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
}
def MipsMemSimm11AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm11";
let SuperClasses = [MipsMemAsmOperand];
@ -519,6 +527,12 @@ def mem_simm9 : mem_generic {
let ParserMatchClass = MipsMemSimm9AsmOperand;
}
def mem_simm9gpr : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm9);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
}
def mem_simm11 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm11);
let EncoderMethod = "getMemEncoding";
@ -707,14 +721,19 @@ class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
let mayLoad = 1;
}
class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
}
class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
// Load/Store Left/Right
let canFoldAsLoad = 1 in
class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,

18
test/MC/Disassembler/Mips/micromips.txt
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@ -346,3 +346,21 @@
0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5)
0x54 0x65 0x09 0xa0 # CHECK: prefx 1, $3($5)
0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
0x60 0x82 0x68 0x08 # CHECK: lbe $4, 8($2)
0x60 0x82 0x60 0x08 # CHECK: lbue $4, 8($2)
0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
0x60 0x82 0x6e 0x08 # CHECK: lwe $4, 8($2)
0x60 0xa4 0xa8 0x08 # CHECK: sbe $5, 8($4)
0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)

18
test/MC/Disassembler/Mips/micromips_le.txt
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@ -346,3 +346,21 @@
0x25 0x60 0x08 0xa6 # CHECK: cachee 1, 8($5)
0x25 0x60 0x08 0xa4 # CHECK: prefe 1, 8($5)
0x65 0x54 0xa0 0x09 # CHECK: prefx 1, $3($5)
0x82 0x60 0x08 0x62 # CHECK: lhue $4, 8($2)
0x82 0x60 0x08 0x68 # CHECK: lbe $4, 8($2)
0x82 0x60 0x08 0x60 # CHECK: lbue $4, 8($2)
0x82 0x60 0x08 0x6a # CHECK: lhe $4, 8($2)
0x82 0x60 0x08 0x6e # CHECK: lwe $4, 8($2)
0xa4 0x60 0x08 0xa8 # CHECK: sbe $5, 8($4)
0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)

3
test/MC/Mips/micromips-control-instructions.s
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@ -41,6 +41,7 @@
# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
# CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@ -76,6 +77,7 @@
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
# CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
sdbbp
sdbbp 34
@ -106,3 +108,4 @@
tlbwr
prefe 1, 8($5)
cachee 1, 8($5)
prefx 1, $3($5)

1
test/MC/Mips/micromips-invalid.s
View File

@ -78,3 +78,4 @@
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
prefx 33, $8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range

24
test/MC/Mips/micromips-loadstore-instructions.s
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@ -44,6 +44,14 @@
# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0]
# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@ -82,6 +90,14 @@
# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
lb $5, 8($4)
lbu $6, 8($4)
lh $2, 8($4)
@ -117,3 +133,11 @@
swm $16, $17, 8($sp)
swp $16, 8($4)
lwp $16, 8($4)
lhue $4, 8($2)
lbe $4, 8($2)
lbue $4, 8($2)
lhe $4, 8($2)
lwe $4, 8($2)
sbe $5, 8($4)
she $5, 8($4)
swe $5, 8($4)

1
test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s
View File

@ -8,4 +8,3 @@
.set noat
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

1
test/MC/Mips/mips32r6/invalid-mips4.s
View File

@ -11,3 +11,4 @@
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s
View File

@ -8,4 +8,3 @@
.set noat
bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction

1
test/MC/Mips/mips64r6/invalid-mips4.s
View File

@ -14,3 +14,4 @@
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled