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[X86][AVX512] Change VCVTSS2SD and VCVTSD2SS node types to keep consistency between VEX/EVEX versions.
AVX versions of the converts work on f32/f64 types, while AVX512 version work on vectors. Differential Revision: https://reviews.llvm.org/D29988 llvm-svn: 295940
This commit is contained in:
Ayman Musa
parent
6b427f77ee
commit
b129f93b10
@ -259,6 +259,23 @@ multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
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MaskingConstraint, NoItinerary, IsCommutable,
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IsKCommutable>;
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// Similar to AVX512_maskable_common, but with scalar types.
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multiclass AVX512_maskable_fp_common<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs,
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dag Ins, dag MaskingIns, dag ZeroMaskingIns,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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SDNode Select = vselect,
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string MaskingConstraint = "",
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InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0,
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bit IsKCommutable = 0> :
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AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
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AttSrcAsm, IntelSrcAsm,
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[], [], [],
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MaskingConstraint, NoItinerary, IsCommutable,
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IsKCommutable>;
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// This multiclass generates the unconditional/non-masking, the masking and
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// the zero-masking variant of the vector instruction. In the masking case, the
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// perserved vector elements come from a new dummy input operand tied to $dst.
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@ -291,6 +308,18 @@ multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
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(X86selects _.KRCWM:$mask, RHS, _.RC:$src0),
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X86selects, "$src0 = $dst", itin, IsCommutable>;
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// Similar to AVX512_maskable_scalar, but with scalar types.
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multiclass AVX512_maskable_fp_scalar<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0> :
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AVX512_maskable_fp_common<O, F, _, Outs, Ins,
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!con((ins _.FRC:$src0, _.KRCWM:$mask), Ins),
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!con((ins _.KRCWM:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm,
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X86selects, "$src0 = $dst", itin, IsCommutable>;
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// Similar to AVX512_maskable but in this case one of the source operands
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// ($src1) is already tied to $dst so we just use that for the preserved
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// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
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@ -6030,27 +6059,40 @@ let Predicates = [HasAVX512] in {
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//===----------------------------------------------------------------------===//
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multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNode> {
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defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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let isCodeGenOnly = 1 in {
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defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode (_.VT _.RC:$src1),
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(_Src.VT _Src.RC:$src2),
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(i32 FROUND_CURRENT)))>,
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EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
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defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _Src.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
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defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode (_.VT _.RC:$src1),
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(_Src.VT (scalar_to_vector
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(_Src.ScalarLdFrag addr:$src2))),
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(i32 FROUND_CURRENT)))>,
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EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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}
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defm rr : AVX512_maskable_fp_scalar<opc, MRMSrcReg, _, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _Src.FRC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2">,
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EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
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let mayLoad = 1 in
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defm rm : AVX512_maskable_fp_scalar<opc, MRMSrcMem, _, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2">,
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EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
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}
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// Scalar Coversion with SAE - suppress all exceptions
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multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNodeRnd> {
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defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
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"{sae}, $src2, $src1", "$src1, $src2, {sae}",
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(_.VT (OpNodeRnd (_.VT _.RC:$src1),
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@ -6062,7 +6104,7 @@ multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTIn
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// Scalar Conversion with rounding control (RC)
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multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNodeRnd> {
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defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
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"$rc, $src2, $src1", "$src1, $src2, $rc",
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(_.VT (OpNodeRnd (_.VT _.RC:$src1),
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@ -6095,39 +6137,36 @@ defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd",
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X86fpextRnd,f32x_info, f64x_info >;
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def : Pat<(f64 (fpextend FR32X:$src)),
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(COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
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(COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
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(VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, FR64X), FR32X:$src)>,
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Requires<[HasAVX512]>;
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def : Pat<(f64 (fpextend (loadf32 addr:$src))),
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(COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
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(VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX512]>;
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def : Pat<(f64 (extloadf32 addr:$src)),
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(COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
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(VCVTSS2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[HasAVX512, OptForSize]>;
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def : Pat<(f64 (extloadf32 addr:$src)),
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(COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
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(COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
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(VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
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Requires<[HasAVX512, OptForSpeed]>;
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def : Pat<(f32 (fpround FR64X:$src)),
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(COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
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(COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
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(VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, FR32X), FR64X:$src)>,
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Requires<[HasAVX512]>;
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def : Pat<(v4f32 (X86Movss
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(v4f32 VR128X:$dst),
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(v4f32 (scalar_to_vector
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(f32 (fpround (f64 (extractelt VR128X:$src, (iPTR 0))))))))),
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(VCVTSD2SSZrr VR128X:$dst, VR128X:$src)>,
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(VCVTSD2SSZrr_Int VR128X:$dst, VR128X:$src)>,
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Requires<[HasAVX512]>;
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def : Pat<(v2f64 (X86Movsd
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(v2f64 VR128X:$dst),
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(v2f64 (scalar_to_vector
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(f64 (fpextend (f32 (extractelt VR128X:$src, (iPTR 0))))))))),
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(VCVTSS2SDZrr VR128X:$dst, VR128X:$src)>,
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(VCVTSS2SDZrr_Int VR128X:$dst, VR128X:$src)>,
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Requires<[HasAVX512]>;
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//===----------------------------------------------------------------------===//
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@ -1851,6 +1851,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VCMPSDZrr_Int, X86::VCMPSDZrm_Int, TB_NO_REVERSE },
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{ X86::VCMPSSZrr, X86::VCMPSSZrm, 0 },
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{ X86::VCMPSSZrr_Int, X86::VCMPSSZrm_Int, TB_NO_REVERSE },
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{ X86::VCVTSS2SDZrr, X86::VCVTSS2SDZrm, 0 },
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{ X86::VCVTSS2SDZrr_Int, X86::VCVTSS2SDZrm_Int, TB_NO_REVERSE },
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{ X86::VCVTSD2SSZrr, X86::VCVTSD2SSZrm, 0 },
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{ X86::VCVTSD2SSZrr_Int, X86::VCVTSD2SSZrm_Int, TB_NO_REVERSE },
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{ X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
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{ X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
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{ X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
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@ -8165,11 +8169,15 @@ static bool hasUndefRegUpdate(unsigned Opcode) {
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case X86::VCVTUSI642SDZrrb_Int:
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case X86::VCVTUSI642SDZrm_Int:
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case X86::VCVTSD2SSZrr:
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case X86::VCVTSD2SSZrrb:
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case X86::VCVTSD2SSZrr_Int:
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case X86::VCVTSD2SSZrrb_Int:
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case X86::VCVTSD2SSZrm:
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case X86::VCVTSD2SSZrm_Int:
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case X86::VCVTSS2SDZrr:
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case X86::VCVTSS2SDZrrb:
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case X86::VCVTSS2SDZrr_Int:
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case X86::VCVTSS2SDZrrb_Int:
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case X86::VCVTSS2SDZrm:
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case X86::VCVTSS2SDZrm_Int:
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case X86::VRNDSCALESDr:
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case X86::VRNDSCALESDrb:
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case X86::VRNDSCALESDm:
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@ -1716,20 +1716,21 @@ def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
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// Convert scalar double to scalar single
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let hasSideEffects = 0, Predicates = [UseAVX] in {
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def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
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(ins FR64:$src1, FR64:$src2),
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(ins FR32:$src1, FR64:$src2),
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"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
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IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
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Sched<[WriteCvtF2F]>, VEX_WIG;
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let mayLoad = 1 in
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def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
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(ins FR64:$src1, f64mem:$src2),
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(ins FR32:$src1, f64mem:$src2),
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"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[], IIC_SSE_CVT_Scalar_RM>,
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XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
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Sched<[WriteCvtF2FLd, ReadAfterLd]>, VEX_WIG;
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}
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def : Pat<(f32 (fpround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
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def : Pat<(f32 (fpround FR64:$src)),
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(VCVTSD2SSrr (COPY_TO_REGCLASS FR64:$src, FR32), FR64:$src)>,
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Requires<[UseAVX]>;
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def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
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@ -1781,14 +1782,14 @@ def Int_CVTSD2SSrm: I<0x5A, MRMSrcMem,
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// SSE2 instructions with XS prefix
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let hasSideEffects = 0, Predicates = [UseAVX] in {
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def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
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(ins FR32:$src1, FR32:$src2),
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(ins FR64:$src1, FR32:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[], IIC_SSE_CVT_Scalar_RR>,
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XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
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Sched<[WriteCvtF2F]>, VEX_WIG;
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let mayLoad = 1 in
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def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
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(ins FR32:$src1, f32mem:$src2),
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(ins FR64:$src1, f32mem:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[], IIC_SSE_CVT_Scalar_RM>,
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XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
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@ -1796,15 +1797,15 @@ def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
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}
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def : Pat<(f64 (fpextend FR32:$src)),
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(VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
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(VCVTSS2SDrr (COPY_TO_REGCLASS FR32:$src, FR64), FR32:$src)>, Requires<[UseAVX]>;
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def : Pat<(fpextend (loadf32 addr:$src)),
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(VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
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(VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
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def : Pat<(extloadf32 addr:$src),
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(VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
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(VCVTSS2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>,
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Requires<[UseAVX, OptForSize]>;
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def : Pat<(extloadf32 addr:$src),
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(VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
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(VCVTSS2SDrr (f64 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
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Requires<[UseAVX, OptForSpeed]>;
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def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
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@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+f16c | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,-f16c | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512VL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c -verify-machineinstrs | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+f16c -verify-machineinstrs | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,-f16c -verify-machineinstrs | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl -verify-machineinstrs | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512VL
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;
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; Half to Float
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@ -1941,25 +1941,25 @@ define <8 x double> @cvt_8i16_to_8f64(<8 x i16> %a0) nounwind {
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; AVX1-LABEL: cvt_8i16_to_8f64:
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; AVX1: # BB#0:
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; AVX1-NEXT: vmovq %xmm0, %rdx
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; AVX1-NEXT: movq %rdx, %r9
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; AVX1-NEXT: movq %rdx, %r8
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; AVX1-NEXT: movl %edx, %r10d
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; AVX1-NEXT: movswl %dx, %r8d
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; AVX1-NEXT: movswl %dx, %r9d
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; AVX1-NEXT: shrq $48, %rdx
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; AVX1-NEXT: shrq $32, %r9
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; AVX1-NEXT: shrq $32, %r8
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; AVX1-NEXT: shrl $16, %r10d
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; AVX1-NEXT: vpextrq $1, %xmm0, %rdi
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; AVX1-NEXT: movq %rdi, %rsi
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; AVX1-NEXT: movl %edi, %eax
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; AVX1-NEXT: movq %rdi, %rax
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; AVX1-NEXT: movl %edi, %esi
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; AVX1-NEXT: movswl %di, %ecx
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; AVX1-NEXT: shrq $48, %rdi
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; AVX1-NEXT: shrq $32, %rsi
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; AVX1-NEXT: shrl $16, %eax
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; AVX1-NEXT: cwtl
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: shrq $32, %rax
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; AVX1-NEXT: shrl $16, %esi
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; AVX1-NEXT: movswl %si, %esi
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; AVX1-NEXT: vmovd %esi, %xmm0
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; AVX1-NEXT: vcvtph2ps %xmm0, %xmm1
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; AVX1-NEXT: vmovd %ecx, %xmm0
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; AVX1-NEXT: vcvtph2ps %xmm0, %xmm2
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; AVX1-NEXT: movswl %si, %eax
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; AVX1-NEXT: cwtl
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; AVX1-NEXT: vmovd %eax, %xmm0
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; AVX1-NEXT: vcvtph2ps %xmm0, %xmm3
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; AVX1-NEXT: movswl %di, %eax
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@ -1968,9 +1968,9 @@ define <8 x double> @cvt_8i16_to_8f64(<8 x i16> %a0) nounwind {
|
||||
; AVX1-NEXT: movswl %r10w, %eax
|
||||
; AVX1-NEXT: vmovd %eax, %xmm0
|
||||
; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
|
||||
; AVX1-NEXT: vmovd %r8d, %xmm5
|
||||
; AVX1-NEXT: vmovd %r9d, %xmm5
|
||||
; AVX1-NEXT: vcvtph2ps %xmm5, %xmm5
|
||||
; AVX1-NEXT: movswl %r9w, %eax
|
||||
; AVX1-NEXT: movswl %r8w, %eax
|
||||
; AVX1-NEXT: vmovd %eax, %xmm6
|
||||
; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6
|
||||
; AVX1-NEXT: movswl %dx, %eax
|
||||
@ -1995,25 +1995,25 @@ define <8 x double> @cvt_8i16_to_8f64(<8 x i16> %a0) nounwind {
|
||||
; AVX2-LABEL: cvt_8i16_to_8f64:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vmovq %xmm0, %rdx
|
||||
; AVX2-NEXT: movq %rdx, %r9
|
||||
; AVX2-NEXT: movq %rdx, %r8
|
||||
; AVX2-NEXT: movl %edx, %r10d
|
||||
; AVX2-NEXT: movswl %dx, %r8d
|
||||
; AVX2-NEXT: movswl %dx, %r9d
|
||||
; AVX2-NEXT: shrq $48, %rdx
|
||||
; AVX2-NEXT: shrq $32, %r9
|
||||
; AVX2-NEXT: shrq $32, %r8
|
||||
; AVX2-NEXT: shrl $16, %r10d
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rdi
|
||||
; AVX2-NEXT: movq %rdi, %rsi
|
||||
; AVX2-NEXT: movl %edi, %eax
|
||||
; AVX2-NEXT: movq %rdi, %rax
|
||||
; AVX2-NEXT: movl %edi, %esi
|
||||
; AVX2-NEXT: movswl %di, %ecx
|
||||
; AVX2-NEXT: shrq $48, %rdi
|
||||
; AVX2-NEXT: shrq $32, %rsi
|
||||
; AVX2-NEXT: shrl $16, %eax
|
||||
; AVX2-NEXT: cwtl
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: shrq $32, %rax
|
||||
; AVX2-NEXT: shrl $16, %esi
|
||||
; AVX2-NEXT: movswl %si, %esi
|
||||
; AVX2-NEXT: vmovd %esi, %xmm0
|
||||
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm1
|
||||
; AVX2-NEXT: vmovd %ecx, %xmm0
|
||||
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm2
|
||||
; AVX2-NEXT: movswl %si, %eax
|
||||
; AVX2-NEXT: cwtl
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm3
|
||||
; AVX2-NEXT: movswl %di, %eax
|
||||
@ -2022,9 +2022,9 @@ define <8 x double> @cvt_8i16_to_8f64(<8 x i16> %a0) nounwind {
|
||||
; AVX2-NEXT: movswl %r10w, %eax
|
||||
; AVX2-NEXT: vmovd %eax, %xmm0
|
||||
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
|
||||
; AVX2-NEXT: vmovd %r8d, %xmm5
|
||||
; AVX2-NEXT: vmovd %r9d, %xmm5
|
||||
; AVX2-NEXT: vcvtph2ps %xmm5, %xmm5
|
||||
; AVX2-NEXT: movswl %r9w, %eax
|
||||
; AVX2-NEXT: movswl %r8w, %eax
|
||||
; AVX2-NEXT: vmovd %eax, %xmm6
|
||||
; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6
|
||||
; AVX2-NEXT: movswl %dx, %eax
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user